Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-08-05
2004-03-16
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S308000, C257S532000
Reexamination Certificate
active
06707091
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor, and more specifically, it relates to a semiconductor device having a capacitor including a lower electrode and an upper electrode opposed to each other through a dielectric layer.
2. Description of the Background Art
A capacitor of a DRAM (dynamic random access memory) is widely known as a capacitor employed in a semiconductor device.
FIG. 5
is a sectional view schematically showing the structure of a capacitor of a conventional DRAM. Referring to
FIG. 5
, the capacitor of the conventional DRAM ha a storage node flower electrode)
104
, a capacitor dielectric layer
105
and a cell plate (upper electrode)
106
.
The storage node
104
is electrically connected to impurity regions serving as source/drain regions formed on a silicon substrate
101
through a plug layer
102
. The plug layer
102
fills up a contact hole formed in an interlayer isolation layer
103
. The storage node
104
is made of polycrystalline silicon doped with phosphorus employed as an n-type impurity. The capacitor dielectric layer
105
, formed to cover the storage node
104
, is made of Ta
2
O
5
. The cell plate
106
is formed to be opposed to the storage node
104
through the capacitor dielectric layer
105
. The cell plate
106
is made of polycrystalline silicon doped with phosphorus employed as an n-type impurity.
In the conventional DRAM, a high potential
107
is supplied to the cell plate
106
and a low potential
108
is supplied to the storage node
104
when a memory cell stores information. A large number of electrons serving as carriers are present in the n-type cell plate
106
. The electrons recede from the storage node
104
having the relatively low potential
108
, and hence a depletion layer having no carriers is formed in the portion of the cell plate
106
in contact with the capacitor dielectric layer
105
. The depletion layer containing no carriers has insulation properties. In practice, therefore, it follows that two dielectric layers including the capacitor dielectric layer
105
and the depletion layer are present between the storage node
104
and the cell plate
106
, to substantially increase the thickness of the capacitor dielectric layer
105
. Thus, the quantity of charges stored in the capacitor is disadvantageously reduced.
SUMMARY OF THE INVENTION
The present invention has been proposed in order to solve the aforementioned problem, and an object thereof is to provide a semiconductor device having a capacitor capable of effectively preventing reduction of capacitance.
The semiconductor device having a capacitor according to the present invention has a capacitor including a lower electrode and an upper electrode opposed to each other through a dielectric layer, and at least either the lower electrode or the upper electrode has a mixed crystal layer of SiGe (silicon germanium) containing a p-type impurity.
In the semiconductor device having a capacitor according to the present invention, at least either the lower electrode or the upper electrode has a mixed crystal layer of SiGe. The mixed crystal layer of SiGe is a material having a smaller quantity of formation of a depletion layer than a layer of Si. Therefore, spreading of a depletion layer can be suppressed in the mixed crystal layer of SiGe for inhibiting the dielectric layer from substantial increase of the thickness, whereby the quantity of charges stored in the capacitor can be prevented from reduction.
Further, majority carriers in the electrode having the mixed crystal layer of SiGe are holes due to the p-type impurity contained therein. Also when a high potential is supplied to such a p-type electrode, therefore, no depletion layer is formed in the portion of the p-type electrode in contact with the dielectric layer. When the mixed crystal layer of SiGe containing a p-type impurity is employed for an electrode supplied with a higher potential, therefore, this electrode can be prevented from formation of a depletion layer.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 6441423 (2002-08-01), Mandelman et al.
patent: 6458645 (2002-10-01), DeBoer et al.
patent: 6507063 (2003-01-01), Coolbaugh et al.
patent: 6511873 (2003-01-01), Ballantine et al.
patent: 6541811 (2003-04-01), Thankur et al.
patent: 2002/0197831 (2002-12-01), Todd et al.
patent: 5-211288 (1993-08-01), None
H.S. Rhee, et al,“Ge-Redistributed Poly-Si/SiGe Stack Gate (GRPSG) for High-Performance CMOSFETs”Symposium on VLSI Technology Digest of Technical Papers, 2001, pp. 61-62, No month given.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
Wilson Allan R.
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