Electronic digital logic circuitry – Multifunctional or programmable – Array
Reexamination Certificate
2002-03-28
2004-04-06
Tran, Anh (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Array
C326S038000, C326S041000
Reexamination Certificate
active
06717436
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a reconfigurable gate array with a number of function blocks. The function blocks are connected to one another via controllable wiring and can be controlled individually, for the respective execution of a specific function. An interface for data and address communication is connected between a processor and the gate array, and to supply configurations, in each case needed to control the function blocks and/or their wiring from a configuration memory.
A reconfigurable gate array of the type is, for example, a known user-programmable gate array or FPGA (field programmable gate array). Such FPGAs are, for example, provided by a module from the XC6200 family, i.e., the XC62xx series (xx=09, 16, 36, or 64) from XILINX® or they are described in Hartenstein and Prasanna: “Reconfigurable Architectures: High Performance by Configware,” Itpress Verlag, D-76607 Bruchsal, Germany, 1997 (ISBN 0-9639887-1-9), p. 147-50.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a reconfigurable gate array, which overcomes the disadvantages of the heretofore-known devices and methods of this general type and which allows wider functions to be implemented than hitherto.
With the foregoing and other objects in view there is provided, in accordance with the invention, a reconfigurable gate array assembly, comprising:
a gate array with a plurality of function blocks connected to one another via controllable wiring, the function blocks being individually controllable, for a respective execution of a specific function;
a first interface for data and address communication between the gate array and a processor;
a second interface for supplying configurations from a configuration memory, in each case needed to control one of the function blocks and the controllable wiring; and
a buffer memory device connected to the second interface for selectively storing configurations from the configuration memory and for direct selective access from the gate array to any configuration stored in the buffer memory device;
the buffer memory device having a reconfiguration controller, operating in accordance with a caching strategy, for removing little-used, unused, or last-used configurations from the buffer memory device to create space for new configurations.
In accordance with an added feature of the invention, the buffer storage device is commonly integrated with the gate array on a common semiconductor chip.
In accordance with a concomitant feature of the invention, the buffer storage device comprises at least one dual-ported memory having a first port for a selective supply of configurations from the configuration memory and for storing the configurations supplied in the double-ported memory, and a second port for allowing the gate array direct selective access to any configuration stored in the dual-ported memory.
In other words, the gate array according to the invention is characterized by a buffer memory device for the selective storage of configurations from the configuration memory and for direct selective access from the gate array to each configuration stored in the buffer memory device.
This solution advantageously provides a reconfigurable, in particular dynamically reconfigurable, integrated circuit with which, even in the case in which the number of function or logic blocks and/or the wiring resources are too small for an implementation of a wider, industrially relevant circuit and/or function, such a wider circuit and/or function can still be implemented.
Advantageously, in this solution, even functions which are represented on an FPGA used as a coprocessor and which can be found only with difficulty in the code of a program, and often can only be loaded inefficiently dynamically onto the FPGA during the running of the program, can be found significantly more easily.
In addition, dynamic displacement of functions onto an FPGA, which in the case of a conventional FPGA is difficult without impairing the overall function, may advantageously be carried out more easily.
In addition, the replacement of a few or unused functions or LRU functions (LRU stands for least recently used), which can be implemented only with difficulty in a cache mechanism with special external memory, separate from the FPGA, may be implemented significantly more easily.
The gate array according to the invention is also advantageous as compared with solutions proposed hitherto for solving the aforementioned problems and which can be summarized in the following points:
Large circuits or functions are partitioned and the functionality is distributed to a plurality of integrated circuits, or the circuits or functions are partitioned and the functionality is divided up over time, that is to say use is made of the possibility of reconfiguring the integrated circuits. The reconfiguration strategy and its time is defined by the user in advance.
Functions which run through automatic placement and routing tools are normally constructed very irregularly. A download strategy is not taken into account by the tools and can therefore be implemented with a great deal of effort.
The same applies to a download strategy.
A specific configuration connection which would be suitable to implement a caching mechanism, is normally not present. Some modules have serial connections, which are too slow, or the configuration connection needs the same resources as, for example, the data input.
Further advantages of the gate array according to the invention are to be seen in the fact that
on a dynamically reconfigurable FPGA module, such as a module from the XC62xx series from XILINX®, by means of the buffer memory a caching memory can be implemented which is preferably and advantageously directly co-integrated.
standard function modules (function macros) are already recognized during the compilation of a program and appropriately incorporated into the run-time program (binary), the macros which are no longer needed or which will be needed very soon with a high probability are already recognized during the compilation in the program graph produced,
the macros are matched to the CLB structures, the geometry of the respective FPGA (as was the case, for example, in the case of the standard cells) and to the routine resources,
because of their regular structure, macros can both be displaced laterally and duplicated,
results are held in the registers of the FPGA and, following the downloading or the displacement of a function, can immediately continue to be used,
one second dual-ported memory or else a plurality thereof is or are therefore connected to the SRAM (static memory with random access) of a CLB device (CLB stands for command line buffer) via a DMA device (DMA stands for direct memory access) likewise integrated on the chip, in such a way that function macros can be kept in reserve, and therefore a concealed reconfiguration can be carried out at any time, irrespective of the status of the program or of the currently used part of the CLB device, dynamic debugging can be carried out during the running of the program without the running of the program being impaired in any way, and registered values=variables can be distributed either point to point or repeatedly.
The invention advantageously permits the efficient use of “memory-organized” FPGAs for reconfigurable systems, for example in the area of custom computing.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a reconfigurable gate array, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
REFERENCES:
patent: 4870302 (1989-09-01), Freeman
patent: 4935734 (1990-06-01), Austin
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5838165 (1998-11-01), Chatter
patent: 6438737 (200
Buchenrieder Klaus
Kress Rainer
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
Tran Anh
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