Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2003-01-16
2004-03-30
Whitmore, Stacy (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06715133
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to integrated circuit chips, and, in particular, to enhancement of reliability of the chip by adding redundant vias.
DESCRIPTION OF THE RELATED ART
An integrated circuit chip comprises a number of active transistors, and perhaps resistors, capacitors, and inductors. These components are electrically coupled by interconnection conductors, or wires, to create a desired function on the chip.
In the early days of semiconductor chips, the interconnection was usually accomplished on two layers of wiring. Aluminum or aluminum alloy was often used for the wiring metallurgy. Interlevel conductors, called vias, were used to electrically couple a signal on one wiring layer to another wiring layer. On the chip, one layer of wiring would predominantly have wires going horizontally when looking down on the chip; the other layer of wiring would predominantly have wires going vertically. For example, if an interconnection required that a signal be routed vertically 100 units and horizontally 45 units, a routing program or a graphics technician would route the signal 100 units on a layer predominantly used for vertical wiring, and 45 units on a second layer which was devoted primarily to horizontal wiring. The program or technician would complete the electrical path by placing a via at the intersection where the signal wire on the upper wiring layer is physically under the signal wire on the lower layer of wiring.
Modern semiconductor chip technology has advanced significantly, and many chips have six or more layers of wiring. Vias are still used to couple signal wire portions on different layers of wiring. Modern chips can easily have over 400,000 signals and over 4,000,000 vias to interconnect the circuits.
Vias are physically very small, the area of a via being limited to the area defined by the conjunction of the signal wiring shapes on the two layers. For example, if the signal wires are 0.5 microns wide, a via would be 0.5 micron wide by 0.5 micron high, at most. In practice, the via might be smaller yet to allow for misregistration of the via on the signal wires, or to allow for other process tolerances. The extremely small size of the vias increases the probability, given normal process defect densities and tolerances, that some of the vias on the chip have defects, and may be much more resistive than would be expected.
Delays in signals on the chip are introduced when the signal wiring is resistive or has resistive portions. A logic circuit driving the signal must charge or discharge some amount of capacitance to bring the signal to a valid logic level. A resistance in series with the signal path limits the current available to charge or discharge the capacitor. Capacitance that must be charged or discharged is accurately calculated by available design automation tools, which examine the signal wires for parasitic capacitance to other signal wires and to supply voltage wires. In addition, inputs of logic circuits driven are, in general, capacitive. Many design automation tools calculate delays for expected resistance and capacitance elements of the signal wiring, including expected resistance of vias. However, an unexpectedly large resistance will invalidate the delay number calculated. Invalid delays caused by process defects will often, but not always, be detected during normal chip testing procedures. If detected, the chip will be rejected, decreasing the yield of the fabrication process. If not detected, faulty operation of the product in the customer's office could occur.
Delay caused by a resistance is largely dependent upon how much capacitance must be charged by current that must flow through the resistor. Many sophisticated techniques are used to calculate, with varying degrees of accuracy, the delay caused by a resistor. For purposes of explanation, a very simple approximation is that the delay caused by a resistor is equal to the value of the resistor times the total capacitance that must be driven through the resistor. This approximation becomes “exact” if a linear voltage is applied at a first side of the resistor and continues ramping forever. The voltage at a second side of the resistor will, after initial transients, be delayed from the voltage at the first side by the resistor value times the value of a capacitor on the second side of the resistor. In practice, for modern logic chips, the approximation's accuracy is limited, but will serve for exemplary purposes.
A signal path will consist of a number of resistive elements and distributed capacitance. The signal may also branch into two or more paths that must be driven. Clearly, resistors near the driver have more capacitance that must be charged through them than a resistor at the end of the signal wire, through which current needs only to charge a small capacitance. Delay calculation error will thus be much larger if an unexpectedly large resistance is introduced near the driver than at the end of the signal.
Some design systems or graphics technicians will, after normal wiring is complete, add redundant vias, where possible, to enhance yield. Expanding some shapes on the signal wire and replacing a single, small via with a larger via, or adding a second via, creates a redundant via. In this invention, a larger via is equivalent to a redundant via. In most designs, wiring areas have a large percentage of available wiring space used by signals, leaving only a portion of the space for such redundant vias. Therefore, not all vias can be made redundant. Yield, therefore, suffers as one or more defective vias are resistive enough to create negative timing margins, or the defective vias are even totally nonconductive.
In many high performance designs, not all signals are candidates for receiving redundant vias. Clock signals, for example, are finely tuned for delay and skew. Addition of redundant vias adds a small amount of capacitance to the signal, which is intolerable on a clock signal. Some signals have insufficient timing margin, and also cannot tolerate the added capacitance of redundant vias.
Present design automation systems do not prioritize creation of redundant vias based on consideration of capacitance that must be driven through the vias.
Therefore, a need exists to provide a method that prioritizes creation of redundant vias on semiconductor integrated circuit chips based on the amount of capacitance that must be driven through the vias.
SUMMARY OF THE INVENTION
The present invention provides a method to increase yield of semiconductor chips by selection of candidate signals capable of having redundant vias added, and prioritizing creation of redundant vias based on the capacitance that must be driven through the vias.
The method of the present invention first eliminates all clock signals from candidacy for replacement of single vias by redundant vias.
The method of the present invention further eliminates all signals with no timing margin or less than a predetermined amount of small timing margin from candidacy for replacement of single vias by redundant vias.
In one embodiment of the present invention, a simple numbering of vias from the drivers on the signals to the receivers is performed. For example, starting at the driver end of each signal wire, the first via encountered would be assigned a “1”; the second would be assigned a “2”, and so on. This would be performed for all signals not eliminated in the first two steps. Upon completion of such numbering, an attempt is made to replace single vias with redundant vias. Where space does not allow replacement of a single via by a redundant via on more than one signal, priority is given to the single via with the lowest assigned number. Obviously, the number given the first via is arbitrary, and could be 0, for example, rather than 1. Furthermore, incrementing need not be by 1. Any numbering scheme indicative of how many vias separate an instant via from the driver is anticipated by this invention.
In another embodiment of the present invention, each via on candidate signals is assigned a value indica
Whitmore Stacy
Williams Robert R.
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