Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-06-26
2004-03-30
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189070, C365S189120, C365S193000, C365S207000, C365S233100, C365S240000
Reexamination Certificate
active
06714464
ABSTRACT:
BACKGROUND
This document relates to memory technology, and, in particular, to a system and method for calibrating sense amplifier enable, or strobe, signals.
In computer memory systems it is important to minimize the time necessary to read data from RAM. When using a RAM array with self-contained read amplifier strobe timing, current methods use a conservative timing estimate obtained from circuit simulation. Since it is a conservative estimate, the timing is slower than what ideally could be used. Another method is to measure the RAM performance and set the timing once using fuses. Such an approach addresses process variations, but once the timing is set, the RAM array does not have the ability to dynamically alter its timing as needed to respond to variations in voltage, temperature or noise. Therefore the strobe tiring must be set conservatively to account for changes in voltage, temperature and noise. What is needed is a system and method for setting strobe timing that reduces the memory cycle as much as possible while adapting to changes in process, voltage, temperature and noise.
SUMMARY
This document discusses a system and method for self-calibration of the strobe timing of the sense-amplifiers of a RAM array. In one method example, the timing of two sense amplifiers used to read the bit-lines of the RAM array is controlled by a Delay Locked Loop circuit (DLL). The timing of a first sense-amplifier strobe is reduced until the sense amplifier fails. The second sense amplifier has adequate timing margin however and is used to actually read the RAM bit-lines. Once the RAM read fails with the first sense amplifier, the DLL lengthens the strobe timing. Once the minimum threshold is set, the second sense amplifier will always read the correct data because of a built-in timing margin between the first and second amplifier. Thus the system constantly optimizes the RAM array read timing with each read cycle even though the minimal time varies.
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Bhatia Ajay
Braganza Michael C.
Morton Shannon V.
Shastry Shashank
Nelms David
Pham Ly Duy
Silicon Graphics Inc.
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