Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Reexamination Certificate
2001-10-09
2004-09-07
Peikari, B. James (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
C711S147000, C710S052000, C710S044000
Reexamination Certificate
active
06789175
ABSTRACT:
TECHNICAL FIELD
The present invention relates to memory devices, and more particularly, synchronous dynamic access memory devices.
BACKGROUND OF THE INVENTION
Conventional dynamic random access memories (DRAMs) perform data transfer operations in sequence. That is, when a read or write command is received and an address is made available, the data transfer operation, either read or write, is performed in its entirety before another command is accepted. Consequently, subsequent commands are delayed by the entire duration of the original data transfer.
The overall time to perform the original data transfer may be significant, because data transfers typically involve several steps, and each step takes time. For example, for a read operation, control logic of the DRAM must decode the command and address, perform precharge and equilibration, connect a row of memory cells to respective digit lines, allow time for sense amplifiers to develop signals; and transfer data from the sense amplifiers to an output data bus. Subsequent commands must wait until these operations are completed before they are accepted by the DRAM. Consequently, reading from and writing to the DRAM must be sufficiently slow to allow the original data transfer to be completed before a subsequent command is provided.
To reduce the amount of delay imposed in sequential data transfer operations, DRAMs can be “pipelined.” In pipelining, each of the above-described steps is performed according to a specific timing sequence. For example, when the original data transfer operation progresses from a first step (e.g., command and address decode) to a second step (e.g., read data), a second data transfer progresses to its first step (command and address decode). Thus, the DRAM's control logic can begin decoding the second command and the DRAM's address decoder can begin decoding the second address while the data from the original data transfer operation is being read from or written to the memory array.
To control the flow of data through a pipelined DRAM, commands and data are transferred synchronously, and such DRAMs are referred to as synchronous DRAMs (“SDRAMs”). In SDRAMs, timing of operations is established relative to the leading edges of a clock signal CLK. At fixed times relative to the leading edges, commands are read by the control logic, addresses are decoded by an address decoder, signals are developed on input and output lines of the memory array, and data is made available for reading or writing at a databus.
In synchronous read operations, an output of data on the data bus results from a read command and an address received at a preceding leading edge of the clock. The delay in number of clock cycles between the arrival of the read command at the control logic input and the availability of the corresponding data at the data bus is the “latency” of the SDRAM. If the output data is available by the second leading edge of the clock following the arrival of the read command, the device is described as a two-latency SDRAM. If the data is available at the third leading edge of the clock following the arrival of the read command, the device is a three-latency SDRAM.
In conventional SDRAMs, latency is only imposed for read operations. In write operations, write commands are supplied simultaneously with data at the data bus. The commands, addresses, and data are transferred to the memory array very quickly, typically within one clock cycle. Typical SDRAMs may thus be described as having no write latency.
FIG. 1
is a block diagram of a conventional synchronous dynamic random access memory
40
(“SDRAM”). The SDRAM
40
has as its central memory element a memory array
42
that is segmented into two banks
44
,
46
. The SDRAM
40
operates under control of a logic controller
48
that receives a system clock signal CLK, a clock-enable signal CKE, and several command signals that control reading from and writing to the SDRAM
40
. Among the command signals are a chip-select signal {overscore (CS)}, a write-enable signal {overscore (WE)}, a column address strobe signal {overscore (CAS)}, and a row address strobe signal {overscore (RAS)}. The overbars for the command signals {overscore (CS)}, {overscore (WE)}, {overscore (CAS)} and {overscore (RAS)} indicate that these signals are low-true signals, i.e., the command signals {overscore (CS)}, {overscore (WE)}, {overscore (CAS)} and {overscore (RAS)} go to a low logic level when true.
In addition to the command signals, the SDRAM
40
also receives addresses from the address bus
52
and receives or outputs data on a data bus
60
. The received addresses may be row or column addresses. In either case, addresses from the address bus
52
are clocked in the SDRAM
40
through an address register or address latch
62
. If an address is a row address, the address is transmitted to the array
42
through a row address path
64
. The row address path
64
includes a row address multiplexer
66
that receives the external row address from the address latch
62
and receives an internal row address from a refresh circuit
67
. The row address multiplexer
66
provides the row addresses to either of two row address latches
70
depending upon the logic state of the bank address BA. The row address latches
70
latch the row addresses and provide the row addresses to respective row decoders
72
. The row decoders
72
take the 11-bit address from the row address latch
70
and activate a selected one of 2,048 row address lines
73
. The row address lines
73
are conventional lines for selecting row addresses of locations in the memory array
42
. As noted above, the following discussion assumes that the row address has been selected and that the selected row is activated.
If the address received at the address latch
62
is a column address, it is transmitted to the I/O interface
54
and the memory array
42
through a column address path
76
. The column address path includes a column address counter/latch
78
that receives or increments, and holds the column address from the address latch
62
, a multiplexer
79
that receives a column address from either address latch
62
or from counter/latch
78
, a pre-decoder
102
and a latch
82
. Depending on whether a particular column access is the result of a new command, or if it is a subsequent access in a burst initiated by a previous command, the multiplexer
79
transmits the appropriate column address to the column decoder
84
, via the column address pre-decoder
102
and latch
82
. For new commands, the multiplexer
79
routes the external address (from the address latch
62
) through to the pre-decoder
102
and latch
82
. A copy is also captured by the column address counter/latch
78
for incrementing on subsequent accesses. If the device
40
has been programmed for a burst length of 2 or greater, and a new column command is not presented to interrupt a column command issued on the previous clock edge, then the counter/latch
78
will increment (or sequence) to the next column address in the burst, and the multiplexer
79
will route the incremented address to the pre-decoder
102
and latch
82
.
The input data path
56
transmits data from the data bus
60
to the I/O interface
54
. The output data path
58
transmits data from the I/O interface
54
to the data bus
60
. Operation of the column address path
76
, input data path
56
, and output data path
58
for a selected sequence of read and write commands will be described below with respect to the timing diagram of FIG.
4
. The logic controller
48
decodes the command signals according to a predetermined protocol to identify read, write, and other commands for execution by the SDRAM
40
.
FIGS. 2 and 3
show clock and command signals and their states for write commands and read commands, respectively. The read and write commands differ only in the state of the write-enable signal {overscore (WE)}. Except for the write-enable signal {overscore (WE)}, the following discussion applies equally to
FIGS. 2 and 3
.
As indicated by the arrow
50
, the
Lee Terry R.
Ryan Kevin J.
Dorsey & Whitney LLP
Micro)n Technology, Inc.
Peikari B. James
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