Semiconductor substract with substantially matched lines

Details Semiconductor substract with substantially matched lines Semiconductor substract with substantially matched lines

2002-07-08

2004-03-30

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S778000, C257S773000, C257S777000

Reexamination Certificate

active

06713879

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to compensation for impedance, capacitance and inductance through matching conductive line lengths on a flip-chip semiconductor device. Particularly, the invention includes at least one ground plane and signal lines having matched lengths to simplify compensation circuitry.
2. State of the Art
Interconnection and packaging related issues are among the factors that determine not only the number of circuits that can be integrated on a chip, but also the performance of the chip. These issues have gained in importance as advances in chip design have led to reduced sizes of transistors and enlarged chip dimensions. The industry has come to realize that merely having a fast chip will not necessarily result in a fast system; the fast chip must also be supported by equally fast and reliable connections. Essentially, the connections, in conjunction with the packaging, supply the chip with signals and power, and redistribute the tightly packed terminals of the chip to the terminals of a carrier substrate such as a printed wiring board.
FIGS. 1 and 2
illustrate a prior art flip-chip semiconductor device
2
in conjunction with a carrier substrate
4
. Flip-chip technology, including its fabrication and use is well known to those of ordinary skill in the art as this technology has been in use and developed for over 30 years. As shown in
FIG. 1
, a flip-chip semiconductor device
2
conventionally comprises an active semiconductor die
6
having an active surface
8
and active surface contacts or bond pads
10
. A dielectric layer
12
, for example, of silicon dioxide or silicon nitride, is formed over the active surface
8
by techniques well known in the art. Vias
14
are defined in dielectric layer
12
, for example, using well-known photolithographic techniques to mask and pattern the dielectric layer
12
and etching same, for example, with buffered HF to expose the active surface contacts or bond pads
10
of the active surface
8
. The bond pads
10
may be connected to traces of an electrical interconnect layer
16
on the dielectric layer
12
in the form of power, ground and signal lines
17
in a well-known manner, for example, by evaporating or sputtering aluminum or an alloy thereof, followed by masking and etching. The signal lines
17
of the electrical interconnect layer
16
enable the relatively compact array of bond pads
10
to be distributed over a broader surface area. Solder bumps
18
, or balls, are placed upon ends of the signal lines
17
of the electrical interconnect layer
16
to enable electrical coupling with contact pads
20
on the carrier substrate
4
, such as a printed wiring board. The flip-chip semiconductor device
2
, with the solder bumps
18
, is inverted so that its front surface
24
faces toward the top surface
26
of the carrier substrate
4
, with each solder bump
18
on the semiconductor device
2
being positioned on the appropriate contact pad
20
of the carrier substrate
4
. The assembly of the flip-chip semiconductor device
2
and the carrier substrate
4
is then heated so as to liquify the solder bumps
18
and thus connect each bond pad
10
on the semiconductor device
2
to an associated contact pad
20
on the carrier substrate
4
.
Because the flip-chip arrangement does not require leads coupled to the active surface of a die and extending beyond the lateral periphery thereof, it provides a compact assembly in terms of the die's “footprint.” In other words, the area of the carrier substrate
4
occupied by the contact pads
20
is, for a given die, the same or less than that occupied by the die itself. Furthermore, the contacts on the die, in the form of solder bumps
18
, may be arranged in a so-called “area array” disposed over substantially the entire front face of the die. Flip-chip bonding, therefore, is well suited for use with dice having large numbers of I/O contacts, in contrast to wire bonding and tape-automated bonding techniques which are far more limiting in terms of the number of bond pads which may reasonably and reliably be employed. As a result, the maximum number of I/O and power/ground terminals available can be increased, and signal and power/ground interconnections can be more efficiently routed on the dice. Examples of methods of fabricating semiconductor die assemblies using flip-chip and other techniques are described in U.S. Pat. No. 6,048,753 to Farnworth et al. (Apr. 11, 2000), U.S. Pat. No. 6,018,196 to Noddin (Jan. 25, 2000), U.S. Pat. No. 6,020,220 to Gilleo et al. (Feb. 1, 2000), U.S. Pat. No. 5,950,304 to Khandros et al. (Sep. 14, 1999), and U.S. Pat. No. 4,833,521 to Early (May 23, 1989).
As with any conductive line carrying a signal, signal lines for integrated circuits generate electromagnetic and electrostatic fields. These electromagnetic and electrostatic fields may affect the signals carried in adjacent signal lines unless some form of compensation is used. It is known to use a ground plane to couple the cross-talk from a signal line on a flip-chip package. An example of a flip-chip semiconductor device using a ground plane is shown and described in U.S. Pat. No. 6,020,637 to Karnezos (Feb. 1, 2000), the disclosure of which is hereby incorporated herein by reference.
Electromagnetic and electrostatic coupling between signal lines, or “cross-talk”, is undesirable because it increases the impedance of the signal lines and may create impedance mismatching and signal delays. The primary factors affecting cross-talk include the surface area of the signal line directed to an adjacent signal line, which includes signal line length, the distance between the signal lines and the dielectric constant (&egr;
r
) of the material between the signal lines. For flip-chip devices, where a large number of contacts with attached signal lines are used to carry signals to various locations for convenient access, impedance can be a significant factor affecting the speed of the system.
One further aspect of flip-chip packaging which adds to the complexity of matching the impedances of the lines is varied line lengths externally between bond pads or other contacts on a die and the solder bumps. To achieve a faster system in a semiconductor environment, conventional wisdom encourages the shortest signal line possible because the shorter the distance the signal needs to travel, the faster it arrives. As a result, when a signal line path is designed for placement on a semiconductor die, or other carrier substrate, it is typically designed with each signal line having an optimal path such that it travels on as short a path as possible, given the overall layout of all the signal line paths. In other words, the signal lines travel in as direct a path as possible from their origins to their destinations, with some variance to accommodate for the paths of other signal lines and positions of various components. For a given die architecture matched to a given I/O array architecture for a specific application, existing signal line lengths are, therefore, varied. Because the impedance of the signal line is, in part, dependent upon the length of the signal line, the impedances of the signal lines of varied length will, therefore, also be varied. Furthermore, due to varied impedance and signal line lengths, signals traveling on those signal lines of different lengths have varied travel times and associated delays.
When the impedance loads on multiple signal lines fed by a common die are equal, the signal strength of the overall system is strongest and signal transfer is most reliable. Impedance mismatches between the signal lines may cause undesirable signal reflections and delays. It is most desirable to have equal impedance loads on each signal line associated with a die, as viewed from the die. To accomplish this, a method used with flip-chip and other type packaging is to add inductors and capacitors to balance the load on each signal line as seen by the semiconductor die. Adding inductors and capacitors, however, while

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