Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-24
2004-07-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S773000
Reexamination Certificate
active
06765256
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device with a capacitor.
2. Description of the Background Art
In recent years, a cylindrical capacitor structure wherein the effective area of an actual capacitor can be made large relative to the projection area of the memory cell has been widely used while, at the same time, miniaturization of the structure of semiconductor devices, in particular of DRAMs (dynamic random access memories), has proceeded. Such a cylindrical capacitor structure has a layered structure provided with a lower electrode formed in a cylinder, a dielectric film covering the surface of the lower electrode and a cell plate.
FIG. 54
is a cross sectional view showing a semiconductor device having a cylindrical capacitor structure according to prior art.
With reference to
FIG. 54
, gate electrodes
104
a
to
104
c
are formed above the main surface
101
a
of a semiconductor substrate
101
with gate insulating films
103
a
to
103
c
intervened there between. Impurity regions
102
a
to
102
d
, as source/drain regions having a predetermined depth, are formed in main surface
101
a
of semiconductor substrate
101
so as to be located on both side faces of gate electrodes
104
a
to
104
c
. An impurity region
102
e
, having a predetermined depth, is formed at a distance away from impurity region
102
d
in main surface
101
a
of semiconductor substrate
101
. Sidewall insulating films
115
a
to
105
c
are formed on the sidewalls of gate electrodes
104
a
to
104
c
. Coating insulating films
106
a
to
106
c
are formed on the top faces of gate electrodes
104
a
to
104
c.
A first interlayer insulating film
107
made of a silicon oxide film is formed so as to cover main surface
101
a
of semiconductor substrate
101
, coating insulating films
106
a
to
106
c
and sidewall insulating films
105
a
to
105
c
. Contact holes
108
a
and
108
b
, reaching impurity regions
102
b
and
102
c
are formed in first interlayer insulating film
107
. Conductor films
109
a
and
109
b
are filled into contact holes
108
a
and
108
b.
A second interlayer insulating film
110
made of a silicon oxide film is formed on first insulating film
107
. A contact hole
111
a
reaching the top face of conductor film
109
b
is formed in second interlayer insulating film
110
. A contact hole
111
b
reaching to impurity region
102
e
formed in main surface
101
a
of semiconductor substrate
101
is formed in first and second interlayer insulating films
107
and
110
. Conductor films
115
a
and
115
b
are filled into contact holes
111
a
and
111
b
. First wire films
112
a
and
112
b
are formed on the top face of second interlayer insulating film
110
so as to make contact with conductor films
115
a
and
115
b.
A third interlayer insulating film
113
made of a silicon oxide film is formed so as to cover second interlayer insulating film
110
, first wire films
112
a
and
112
b
. A contact hole
114
reaching conductor film
109
a
formed in first interlayer insulating film
107
is formed in second and third interlayer insulating films
110
and
113
. A conductor film
116
is filled into contact hole
114
.
A fourth interlayer insulating film
118
made of a silicon oxide film is formed on third interlayer insulating film
113
. A hole
119
reaching conductor film
116
formed in third interlayer insulating film
113
is formed in fourth interlayer insulating film
118
. A cylindrical lower storage node electrode
120
is formed so as to cover the side face and the bottom face of hole
119
wherein lower storage node electrode
120
makes contact with conductor film
116
. A dielectric film
121
is formed so as to cover the surface of lower storage node electrode
120
and a portion of the top face of fourth interlayer insulating film
118
. An upper cell plate electrode
122
is formed so as to cover dielectric film
121
and so as to completely fill in the inside of hole
119
. Lower storage node electrode
120
, dielectric film
121
and upper cell plate electrode
122
form a cylindrical capacitor in a semiconductor device.
A fifth interlayer insulating film
123
made of a silicon oxide film is formed so as to cover upper cell plate electrode
122
and fourth interlayer insulating film
118
. A contact hole
152
a
penetrating through upper cell plate electrode
122
and dielectric film
121
so as to reach the inside of fourth interlayer insulating film
118
is formed in fifth interlayer insulating film
123
. The bottom face of contact hole
152
a
is defined by fourth interlayer insulating film
118
. A contact hole
152
b
reaching first wire film
112
b
formed on the top face of second interlayer insulating film
110
is formed in third, fourth and fifth interlayer insulating films
113
,
118
and
123
. Conductor films
153
a
and
153
b
are filled into contact holes
152
a
and
152
b
. Conductor film
153
a
is connected to the sidewall of upper cell plate electrode
122
resulting from the formation of contact hole
152
a
. Second wire films
154
a
and
154
b
are formed on the top face of fifth interlayer insulating film
123
so as to make contact with conductor films
153
a
and
153
b.
In a semiconductor device having such a cylindrical capacitor, it is necessary to increase the height of the capacitor in order to maintain the capacitance of the capacitor while reducing the size of the memory cell. Therefore, the height of fourth interlayer insulating film
118
tends to increase and the distance between the top face of fifth interlayer insulating film
123
and first wire film
112
b
becomes greater due, in particular, to this tendency.
In addition, for the purpose of setting upper cell plate electrode
122
at a predetermined potential, second wire film
154
a
provided on fifth interlayer insulating film
123
and upper cell plate electrode
122
are connected by conductor film
153
a
. Therefore, it is necessary to form contact hole
152
a
into which conductor film
153
is filled. On the other hand, for the purpose of supplying a signal to impurity region
102
e
and for fixing the potential thereof, second wire film
154
b
provided on fifth interlayer insulating film
123
and first wire film
112
b
provided on second interlayer insulating film
110
are connected by conductor film
153
b
. Therefore, it is necessary to form contact hole
152
b
into which conductor film
153
b
is filled.
These contact holes
152
a
and
152
b
are formed in the same etching step, after the provision of fifth interlayer insulating film
123
, in order to reduce the number of manufacturing steps. Then, this etching step is carried out until contact hole
152
b
reaches first wire film
112
b
. Therefore, contact hole
152
a
first reaches the top face of upper cell plate electrode
122
and, after that, upper cell plate electrode
122
continuously undergoes etching until contact hole
152
b
reaches first wire film
112
b
. As a result of this, as shown in
FIG. 54
, a formation is obtained wherein contact hole
152
a
penetrates through upper cell plate electrode
122
so as to reach the inside of fourth interlayer insulating film
118
.
In the case that contact hole
152
a
penetrates through upper cell plate electrode
122
in such a manner, and the amount of penetration is great, a problem arises wherein conductor film
153
a
is short circuited to, for example, first wire film
112
a.
In addition, the area of contact between conductor film
153
a
filled into contact hole
152
a
and upper cell plate electrode
122
is only the sidewall of upper cell plate electrode
122
resulting from the formation of contact hole
152
a
and, therefore, the area of contact is small. In addition, in the case that conductor film
153
a
is formed by means of sputtering, the coverage of film formation is insufficient on the sidewall of upper cell plate electrode
122
. Furthermore, in the case that the sidewall of uppe
Dokan Takashi
Takeuchi Masahiko
McDermott & Will & Emery
Prenty Mark V.
Renesas Technology Corp.
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