Dynamically reconfiguring clock domains on a chip

Details Dynamically reconfiguring clock domains on a chip Dynamically reconfiguring clock domains on a chip

2002-06-28

2004-05-18

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S729000, C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06738963

ABSTRACT:

BACKGROUND
1. Field
Embodiments of the invention relate to the field of clock architectures. More particularly, embodiments of the invention relate to dynamically reconfiguring clock domains on a chip.
2. Description of Related Art
Since the advent of the integrated circuit (IC), circuit components have become smaller and smaller. An IC may include millions of components packed into an incredibly small package. With each new generation of smaller integration, more functionality, and therefore more value, can be derived from ICs. Reliably manufacturing these highly integrated ICs, however, presents significant design challenges.
In particular, designing ICs that meet timing constraints can be particularly difficult. An IC may include tens of thousands of registers that need to be connected to one or more clock sources. For each clock “tick”, or clock transition, thousands of registers have to operate in concert. A complex network is needed to propagate the clock signal to each of the registers. If the difference in propagation delay through two different paths in the network is too large or too small, errors may occur that can cause the entire IC to fail. Those skilled in the art will be familiar with numerous processes for synthesizing clock networks, or clock tree solutions.
Conventional integrated circuits (ICs) use a clock signal and branch it out through a series of buffers to form a plurality of clock signals. The structure of the branching of the clock signal is called a “clock tree.” One or more clock trees can be present in a single IC. The clock signals at any level of the clock tree are sent to various synchronous components of the IC to coordinate the functions of these components. For various reasons, however, any two clock signals, even at the same level of the same clock tree, may be slightly different or offset from each other. This difference in clock signals is called “clock skew”.
Clock skew has several causes. For example, the buffers between levels in the clock tree typically introduce a delay between their input and output clock signals, so clock signals at different levels of the clock tree are usually naturally skewed from each other. Additionally, the load experienced by one clock signal may introduce a delay into the clock signal different from that of another load on another clock signal. Furthermore, changes in temperature, different applied voltages and differing semiconductor fabrication processes can affect the clock skew.
Common IC fabrication techniques try to minimize clock skew by resizing buffers in the clock tree to move some of the clock signals forward or backward or by adding redundant loads to the circuits to balance the loading of the clock tree. Either technique alters the delay of some of the clock signals by a specified amount that is determined by analysis of the timing of the clock signals. With temperature changes, different applied voltages, differing silicon fabrication processes and/or inadequate tolerances in the silicon fabrication processes, the clock skew can even vary significantly from the nominal value. Due to this variation in clock skew, such ICs will often fail speed testing and not meet performance targets. As a result, IC fabrication yields will be low and costs will be high.
Further, as ICs continue to become more complex, having tens of thousand of registers which may be clocked by several different source clocks, at several different clock frequencies, through gated clocks, inverted clocks, etc., the processing time and expense required to meet continually more stringent design constraints using known approaches is becoming increasingly prohibitive. Moreover, due to the ever increasing complexity of newer ICs, low skew clock distribution becomes more and more difficult to achieve. Normally, when an IC is designed, clock domains are chosen with a size that can achieve the desired clock skew, and synchronization logic is added on the signals that cross the clock domains. This synchronization logic adds additional latency on the signals that cross the clock domain partitions.
This clock domain partitioning is typically done before fabricating the chip, since choosing a large clock domain could result in clock skew problems in the real silicon that is very expensive to fix with another revision of the IC. The difficulty is that the timing models that are used to design the clock tree are usually not accurate enough with respect to the real silicon to design a large clock tree with little clock skew.


REFERENCES:
patent: 5452239 (1995-09-01), Dai et al.
patent: 6127874 (2000-10-01), Wakabayashi et al.
patent: 6340905 (2002-01-01), Schultz
patent: 6367060 (2002-04-01), Cheung et al.
patent: 2002/0040458 (2002-04-01), Dervisoglu et al.

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