Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-09-22
2004-04-13
Tran, Minh Loan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S516000, C257S538000, C257S543000
Reexamination Certificate
active
06720621
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. HEI 11(1999)-322772 filed on Nov. 12, 1999, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a SOI semiconductor device and a fabrication process thereof. More particularly, the present invention relates to a SOI semiconductor device of a voltage control type formed on a SOI substrate, and a fabrication process thereof.
2. Description of Related Art
Resistors and capacitors are commonly used in electric circuits for dealing with analogue signals, such as filters and RC delay lines. In an integrated circuit, the resistor is typically implemented with a diffusion layer formed in a semiconductor substrate or a conductive layer such as a gate electrode of polysilicon, as a passive resistor. The capacitor is utilized gate capacitance of the MOS transistor, junction capacitance, capacitance between two conductive layers isolated by a dielectric film, and the like.
As shown in FIG.
7
(
a
), for example, a MOS transistor is used as a variable resistance element. Voltage Vc is applied to a gate electrode
30
formed on a p-type semiconductor substrate
33
, and voltages Vi and Vo are applied to diffusion layers
31
which are source/drain regions, respectively. By varying the gate voltage Vc so that (Vo−Vi)<<(Vc−Vth), the resistance value of a channel
34
can be changed. The MOS transistor, when used as a variable resistance element, can also serve as a capacitor due to a gate oxide
32
sandwiched between the gate electrode
30
and the semiconductor substrate
33
. Accordingly, an RC circuit can be constituted by combining the resistance with the capacitance.
Japanese Unexamined Patent Publication No. HEI 9(1997)-232522 proposes the use of a junction FET (JFET)
40
formed on a bulk semiconductor substrate, as a variable resistance element. A resistance element
43
is connected between source/drain terminals
41
and
42
of the JFET
40
, so that the JFET, free from the influence of a bias voltage between the source/drain regions, can be used as a variable resistance element, which shows a substantially constant resistance value under a gate bias voltage.
For conventional resistors and capacitors as mentioned above, however, the resistor and capacitor values can not be electrically adjusted. The value of a resistance using a channel in the MOS transistor depends on the mobility of electric charge in an inversion layer, which is subject to the resistor surface condition and interface imperfections. Also, their values are determined by the physical characteristics of material used and the design of circuits. Therefore, the resistor and capacitor are passive in a sense.
Furthermore, the variable range of the resistance value is restricted when the channel of the MOS transistor is used as a resistor. This is because the range of voltage showing the linear portion of the I−(Vo−Vi) curve is small, as shown by the relation between the electric current and the voltage (Vo−Vi) applied to the diffusion layers
31
of the MOS transistor and by the following formula:
I
=
β
×
(
Vc
-
Vth
=
1
2
·
(
Vo
-
Vi
)
)
·
(
Vo
-
Vi
)
≈
β
×
(
Vc
-
Vth
)
·
(
Vo
-
Vi
)
R
≅
1
β
×
(
Vc
-
Vth
)
The JFET
40
, shown in
FIG. 8
, also has the same drawback that the linear portion of the I−(Vo−Vi) curve is limited to a narrow range.
SUMMARY OF THE INVENTION
The present invention is conceived in view of the above circumstances and an object thereof is to provide a SOI semiconductor having a variable resistance element whose resistance value can be varied greatly, i.e., having a control electrode by which its electric characteristics can be controlled.
Accordingly, the present invention provides a SOI semiconductor device comprising: a resistor body which is formed of a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film and which is dielectrically isolated by an insulating film, wherein a resistance value of the resistor body is set to be a predetermined value by the concentration of impurities contained in the top semiconductor layer and by the dimension of the resistor body.
Also, the present invention provides a process of fabricating a SOI semiconductor device comprising the step of: setting a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film to have a predetermined impurity concentration and a predetermined dimension, thereby controlling a resistance value of a resistor body formed of the top semiconductor layer.
Furthermore, the present invention provides a SOI semiconductor device comprising: an electrically variable resistor body which is formed of a top semiconductor layer in a SOI substrate having an embedded dielectric film and the top semiconductor layer formed on the embedded dielectric film and which has a control electrode disposed on the top semiconductor layer with intervention of a dielectric film, wherein the resistor body is partially depleted by the control electrode to form a neutral region through which electric current flows, the resistor body has highly concentrated diffusion layers of a first conductive type at both ends in a conduction direction, and both side walls of the resistor body along the conduction direction are junction-isolated by highly concentrated diffusion layers of a second type.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
REFERENCES:
patent: 3683491 (1972-08-01), Nelson et al.
patent: 4263518 (1981-04-01), Ballatore et al.
patent: 4510517 (1985-04-01), Tanabe et al.
patent: 5767757 (1998-06-01), Prentice
patent: 5872381 (1999-02-01), Kato et al.
patent: 5930638 (1999-07-01), Reedy et al.
patent: 5949115 (1999-09-01), Yamazaki et al.
patent: 6100565 (2000-08-01), Ueda
patent: 6180984 (2001-01-01), Golke et al.
patent: 61-198912 (1986-09-01), None
patent: 02-039563 (1990-02-01), None
patent: 4-67666 (1992-03-01), None
patent: 4-93160 (1992-08-01), None
patent: 5-114699 (1993-05-01), None
patent: 7-58291 (1995-03-01), None
patent: 09-064320 (1997-03-01), None
patent: 9-181262 (1997-07-01), None
patent: 9-232522 (1997-09-01), None
patent: 11-74531 (1999-03-01), None
Japanese Office Action dated Aug. 12, 2003.
Copy of EP Search Report dated Jun. 5, 2003.
Nixon & Vanderhye P.C.
Sharp Kabushiki Kaisha
Tran Minh Loan
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