Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2002-12-06
2004-09-28
Bataille, Pierre (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C713S340000, C713S323000
Reexamination Certificate
active
06799244
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a technique for storage control, and in particular to a technique effectively applicable to a storage control unit or the like having a nonvolatile cache memory for temporarily storing user data.
Current market trends call for higher performance, larger capacity and lower cost storage units. In a redundant array of inexpensive disks (RAID), a plurality of disk units are configured in array. At the time data is written, a copy of the data is often written to a disk unit different from the one for storing the original write data. By doing so, in case of a fault in a disk unit in the array, the data in the defective disk unit can be “repaired” by the data in the redundant disk units, thereby improving reliability and maintainability of the disk units. With RAID, however, though the data reliability is improved, the operation of writing the redundant data increases the processing time, and therefore the write performance deteriorates.
For this reason, a write cache technique is indispensable for supporting RAID in the prior art. The write cache is mounted in the controller and the data are temporarily written to it. In response to the write request from the host, the data is written in this cache. Completion of the write operation is reported to the host at the same time that the data is written in the cache. Thus, the redundant data are generated, the write data and the redundant data are stored in the disk units asynchronously with the I/O processing for the host, thus preventing the deteriorated performance of the write operation.
SUMMARY OF THE INVENTION
The conventional method described above uses a technique for generating the redundant data and writing the write data and the redundant data into the disk units asynchronously with the host I/O processing. This technique, though providing improved responsiveness, cannot improve the processing performance of the control unit.
In addition, the use of the write cache is accompanied by the reporting of the completion of the write operation to the host at the same time that the data is written in the cache. This causes host data not reflected in the disk units to exist in the cache. To prevent data loss upon the occurrence of a fault such as a sudden power failure, therefore, the write cache is required to be nonvolatile. At the same time, not only the user data, but also the information for managing the user data is required to be stored in the write cache or other nonvolatile memory.
Such a write cache or a nonvolatile memory is located outside the processor. The access from the processor to the write cache or the nonvolatile memory, therefore, is slower than the access to the local memory in the processor. This also leads to a deterioration in processing performance.
This invention provides a subsystem which includes a plurality of storage units and a storage control unit interposed between the storage units and a host computer. The storage control unit controls the storage units based on an instruction from the host computer or controls the storage unit with a RAID protocol. The storage control unit includes a nonvolatile cache mechanism for storing the user data temporarily, and the management information for the user data in the cache is stored in both a low-speed nonvolatile memory and a high-speed volatile memory. Normally, the management information in the high-speed volatile memory is accessed at high speed. At the time of a sudden power failure or the like fault, data loss is prevented by the user data/management information in the nonvolatile memory.
To realize these control functions based on the control logic of a storage control unit, the invention provides a subsystem which writes the user data management information in both a low-speed nonvolatile memory and a high-speed volatile memory, which accesses the management information in the high-speed volatile memory under normal conditions, but accesses the management information in the nonvolatile memory in case of a sudden fault such as power failure. The system also restores the accessed information in the volatile memory.
REFERENCES:
patent: 4916605 (1990-04-01), Beardsley et al.
patent: 4920478 (1990-04-01), Furuya et al.
patent: 5133060 (1992-07-01), Weber et al.
patent: 5437022 (1995-07-01), Beardsley et al.
patent: 5778426 (1998-07-01), DeKoning et al.
patent: 5867702 (1999-02-01), Lee
patent: 6154838 (2000-11-01), Le et al.
patent: 6233680 (2001-05-01), Bossen et al.
patent: 6233697 (2001-05-01), Yamamoto
patent: 6243789 (2001-06-01), Hasbun et al.
patent: 6304946 (2001-10-01), Mason
patent: 6336161 (2002-01-01), Watts
patent: 6356978 (2002-03-01), Kobayashi et al.
patent: 6463507 (2002-10-01), Arimilli et al.
patent: 6467029 (2002-10-01), Kitayama
patent: 6550019 (2003-04-01), Ahrens et al.
patent: 2001/0037475 (2001-11-01), Bradshaw et al.
patent: 06028108 (1994-04-01), None
patent: 07056694 (1995-03-01), None
patent: 07121311 (1995-12-01), None
HandyThe Cache Memory Book2nd edition, Academic Press Inc., p. 89 (1998).
Varma et al. “Destage algorithms for Disk arrays with Non-volital Caches,” ACM 0-89791-698-0/95/0006 (1995).
Ishikawa Atsushi
Tanaka Rie
Bataille Pierre
Townsend and Townsend / and Crew LLP
LandOfFree
Storage control unit with a volatile cache and a... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Storage control unit with a volatile cache and a..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Storage control unit with a volatile cache and a... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3215064