Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Reexamination Certificate
2001-10-12
2004-01-13
Pham, Long (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
C438S257000, C438S296000, C438S267000, C438S592000, C438S594000, C438S589000
Reexamination Certificate
active
06677224
ABSTRACT:
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating flash memories.
BACKGROUND OF THE INVENTION
The semiconductor industry has been advanced to the field of Ultra Large Scale Integrated (ULSI) technologies. The fabrication of the nonvolatile memories also follows the trend of the reduction of the size of a device. The nonvolatile memories include various types of devices, such as EAROM (electrically alterable read only memory), EEPROM (electrically erasable programmable read only memory), EEPROM-EAROMs and non-volatile SRAMs. Different types of devices have been developed for specific applications requirements in each of these segments. These parts have been developed with a focus on the high endurance and high-speed requirements. Various nonvolatile memories have been disclosed in the prior art. For example, Mitchellx has proposed EPROMs with self-aligned planar array cell. In this technique, buried diffusion self-aligned to the floating gate avalanche injection MOS transistors are used for the bit lines. Cross point array technology has been disclosed. The self-aligned source and drain will allow this device to be optimized even further for programming speed. See A. T. Mitchellx, “A New Self-Aligned Planar Cell for Ultra High Density EPROMs”, IEDM, Tech. pp. 548-553, 1987”.
Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge on and removing the charges from the floating gate. One of the applications of flash memory is BIOS for computer. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. Bergemont proposed another cell array for portable computing and telecommunications application, which can be seen in Bergmont et al., “Low Voltage NVG™: A New High Performance 3 V/5 V Flash Technology for Portable Computing and Telecommunications Applications”, IEEE Trans. Electron Devices, vol. ED-43, p. 1510, 1996. This cell structure is introduced for low voltage NOR Virtual Ground (NVG) flash memory having fast access time. In the flash array schematic, field oxides (FOX) are formed between cells such that a poly extension on FOX of each cell provides adequate gate coupling ratio. Bergmont also mentioned that the portable telecommunications and computing have become a major driving force in the field of integrated circuits. In the article, the access time is one of the key concerns for low voltage read operation. The NVG array uses select devices to achieve a fast access time by reducing the pre-charge time to that of a single segment rather than the full bit-line.
The formation of nonvolatile memories toward the trends of low supply power and fast access, because these requirements are necessary for the application of the mobile computing system. Flash memory needs the charges to be hold in the floating gate for a long periods of time. Therefore, the dielectric that is used for insulating the floating gate needs to be high performance. At present, the low voltage flash memory is applied with a voltage of about 3V or 5V during charging or discharging the floating gate. As known in the art, tunneling is a basic technology in charging or discharging. In order to attain high tunneling efficiency, the thickness of the dielectric between the floating gate and substrate have to be scaled down due to the supply voltage is reduced.
U.S. Pat. No. 6,180,459 to Sheu, entitled “Method for fabricating a flash memory with shallow trench isolation”, filed on Jan. 8, 1999. The prior art disclosed a method for fabricating a flash memory comprising forming a shallow trench isolation (STI) structure is also formed in the method. A further U.S. Pat. No. 6,172,395 to Chen, et al., entitled “Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby” and assigned to Taiwan Semiconductor Manufacturing Company (Hsin-Chu, TW). U.S. Pat. No. 6,281,103 to Doan entitled “Method for fabricating gate semiconductor”. The prior art disclosed a method for fabricating floating gate semiconductor devices, such as flash EEPROMs, and flash EEPROM memory arrays, is provided. The method includes providing a semiconductor substrate and forming active areas on the substrate. Each active area includes elements of a field effect transistor (FET) including a source, a drain, a channel region, and a gate dielectric layer. Trench isolation structures are also formed in the substrate for electrically isolating the active areas. In addition, a conducive layer (e.g., polysilicon) is deposited on the active areas, and chemically mechanically planarized to an endpoint of the trench isolation structures to form self-aligned floating gates on the active areas. Control gate dielectric layers, and control gates are then formed on the floating gates.
SUMMARY OF THE INVENTION
The object of the present invention is to form a stacked gate for flash devices.
The further object of the present invention is to increase the coupling ratio of flash devices.
The method of the present invention includes the steps of forming doped regions in the semiconductor substrate. A pad oxide layer is formed on the semiconductor substrate. A masking layer is formed on the pad oxide layer. A masking layer, the pad oxide layer and the semiconductor substrate are patterned to form a trench therein. A gap-filling material is refilled into the trench and over the semiconductor substrate. A portion of the gap-filling material is removed to upper surface of the masking layer. Next step is to remove the masking layer. A first conductive layer is formed along the surface of the substrate, then removing a portion of the first conductive layer to expose an upper surface of the gap-filling material. An inter polysilicon dielectric layer is formed on the first conductive layer and a second conductive layer is formed on the inter polysilicon dielectric layer. Wherein the masking layer is removed by hot phosphorus acid solution, the inter polysilicon dielectric layer comprises ONO (oxide
itride/oxide) and ON (oxide
itride). The first conductive layer comprises polysilicon and the second conductive layer comprises polysilicon. Further, the gap-filling material is removed by chemical mechanical polishing (CMP). The first polysilicon layer is removed by chemical mechanical polishing (CMP).
REFERENCES:
patent: 5733383 (1998-03-01), Fazan et al.
patent: 5767005 (1998-06-01), Doan et al.
patent: 6054733 (2000-04-01), Doan et al.
patent: 6180459 (2001-01-01), Sheu
patent: 6281103 (2001-08-01), Doan
patent: 6448606 (2002-09-01), Yu et al.
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