Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-04-21
2004-05-04
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S154000, C365S189090
Reexamination Certificate
active
06731530
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a shadow RAM (Random Access Memory) cell using a ferroelectric capacitor, a non-volatile memory device and a controlling method therefor. More specifically, the present invention relates to a shadow RAM in which each memory cell is constituted of an unloaded four-transistor type SRAM (Static RAM) cell added with ferroelectric capacitors and in which a high speed reading/writing operation is carried out by use of the unloaded four-transistor type SRAM when an electric power is being supplied and a non-volatile memory is realized by use of the ferroelectric capacitors when no electric power is supplied.
Heretofore, various shadow RAMs constituted of a combination of the ferroelectric capacitors and the SRAM cell have been proposed. When an electric power is being supplied, these shadow RAMs can store information in the SRAM cell, and can carry out the reading/writing operation of a high speed comparable to that obtained in a conventional SRAM. In a store operation before the electric power is shut off, the information stored in the SRAM cell is transferred into a polarization direction in the ferroelectric capacitor, so that when no electric power is supplied, a non-volatile memory is realized. In other words, the shadow RAM using the ferroelectric capacitor is a memory device having two features, the non-volatile feature of the ferroelectric capacitor and the high speed operation of the SRAM.
For example, a shadow RAM using a ferroelectric capacitor, as disclosed in Japanese Patent Application No. Heisei 11-099534 (published as JP-A-2000-293989), has a memory cell structure as shown in
FIG. 2. A
flipflop
3
is constituted by connecting an output of each of two inverters
1
and
2
to an input of the other inverter. Two storage nodes Q
0
and Q
1
of the flipflop are connected to an inverted bit line BLN and a non-inverted bit line BLT through NMOS transistors M
0
and M
1
acting as an access transistor, respectively. The inverted bit line BLN and the non-inverted bit line BLT are paired, and are connected at their end to a sense amplifier (not shown) for comparing respective voltages on the inverted and non-inverted bit lines to each other.
Furthermore, the bit lines are connected to a writing circuit (not shown) for selectively connecting either of the pair of bit lines to a ground potential in a writing operation, and a precharge circuit (not shown) for precharging the bit lines to either a power supply voltage or the ground potential. Respective gate electrodes of the NMOS transistors M
0
and M
1
are connected to a common word line WL. The word line WL is connected to a decoder circuit (not shown) for selectively driving one word line to be accessed in accordance with an address signal. Ferroelectric capacitors F
0
and F
1
having their one end connected to a common plate line PL are connected to the storage nodes Q
0
and Q
1
, respectively. The plate line PL is connected to a plate line driving circuit for maintaining the plate line at Vcc/2 in a power supply condition excluding a store operation and a recall operation.
Now, an operation of the prior art shadow RAM using the ferroelectric capacitors will be described. Incidentally, it would be apparent that the information writing and reading operations for the flipflop
3
is similar to those in the conventional SRAM in the prior art. In an idling operation accompanied with neither a reading nor a writing, all of the word lines are pulled down, the bit lines are precharged to an appropriate potential, and the writing circuit is stopped, so that information in the flipflop is retained.
In order to write information into the flipflop
3
, a selected word line WL is pulled up by action of the address decoder, and simultaneously, the writing circuit is driven to bring one of the pair of bit lines BLT and BLN to a low level in accordance with data to be written. When the word line is pulled up, the MOS transistors M
0
and M
1
are turned on. Since the writing circuit has a driving capability sufficiently larger than that of the inverters
1
and
2
, the storage node connected through the MOS transistor to the bit line pulled down by the writing circuit, will be pulled down to the ground potential. Simultaneously, the other storage node is pulled up to the power supply voltage, so that the flipflop becomes stabilized.
In order to read the data from the flipflop
3
, after the pair of bit lines are precharged to a high level, a word line is selected, and a potential difference appearing between the selected pair of bit lines is amplified by the sense amplifier. When the word line is pulled up, the MOS transistor interconnecting between the storage node of the low level and the bit line is turned on, so that the bit line concerned starts to drop. The other bit line maintains the high level, since the MOS transistor is not turned on. By discriminating the potential difference between the pair of bit lines by action of the sense amplifier, the information stored in the flipflop is read out.
Now, a store operation will be described with reference to FIG.
3
and FIG.
4
.
FIG. 3
illustrates a hysteresis on a Q-V plane of the ferroelectric capacitors F
0
and F
1
, and
FIG. 4
is a timing chart illustrating waveforms on various parts in the store operation. When the electric power is shut off, the data stored in the flipflop is transferred to the polarization direction of the ferroelectric capacitors F
0
and F
1
. This operation is called “store”. This store operation is triggered by a drop of the power supply voltage or a store signal supplied before the shutoff of the electric power. The store operation will be carried out in the following procedures:
First, when the store operation starts, the plate line PL is at Vcc/2, so that in accordance with the data stored in the flipflop
3
, −Vcc/2 is applied across one of the ferroelectric capacitors connected to the storage node of 0V, while Vcc/2 is applied across the other ferroelectric capacitor connected to the storage node of the power supply voltage (Vcc).
Here, voltages Vc0 and Vc1 applied across the ferroelectric capacitors F
0
and F
1
, respectively, are defined to be a potential difference between one terminal connected to the plate line PL and the other terminal connected to the storage node Q
0
or Q
1
, by considering the potential at the one terminal connected to the plate line PL as a reference.
Next, the plate line PL is pulled up to Vcc. At this time, in the ferroelectric capacitor previously applied with Vcc/2, the voltages at opposite ends of that ferroelectric capacitor become Vcc, with the result that the voltage across the ferroelectric capacitor becomes 0V. −Vcc is applied across the other ferroelectric capacitor, so that the condition of the other ferroelectric capacitor moves to a point C in the hysteresis loop shown in FIG.
3
.
Thereafter, the plate line PL is pulled down to 0V. At this time, Vcc is applied across the ferroelectric capacitor connected to the storage node of Vcc, so that the ferroelectric capacitor moves to a point A in the hysteresis loop shown in FIG.
3
. Simultaneously, the ferroelectric capacitor that was at the point C moves to a point D, so that a negative remanent polarization is held.
Finally, the electric power is shut off. After the shutoff of the electric power, each node is converged to the ground potential. Accordingly, the ferroelectric capacitor that was at the point A finally moves to a point B, so that a positive remanent polarization is held. Since the ferroelectric capacitor can hold the remanent polarization not less than ten years in a condition in which no voltage is applied, the conventional shadow RAM using the ferroelectric capacitor can realize a non-volatile memory.
Next, the recall operation will be described with timing charts of various parts shown in FIG.
5
. When the electric power is turned on, the data held in the ferroelectric capacitors is transferred to the flipflop. This operation is called “recall”. When the electric
Miwa Tohru
Toyoshima Hideo
Foley & Lardner
Ho Hoai
NEC Corporation
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