Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2002-11-19
2004-07-06
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S185210
Reexamination Certificate
active
06760265
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a non-volatile memory cell read amplifier, applicable, in particular, to EPROM, EEPROM, and FLASH EEPROM memories. The present invention relates more particularly to a read amplifier with a differential output stage.
BACKGROUND OF THE INVENTION
To read data present in a non-volatile memory cell, the programmed or erased state of which determines the value of the data saved in the memory cell, it is common to use a read amplifier to detect the programmed or erased state of the cell by comparing a current passing through the cell with a reference current. The programed state corresponds conventionally to the storage of a 0 and the erased state to the storage of a 1, or vice-versa. Some known read amplifiers comprise an output stage formed by an inverting gate, while others comprise a differential output stage.
A prior art read amplifier with a differential output stage is represented in FIG.
1
. In this figure and in the rest of the present application, PMOS type transistors are designated by references starting by “TP” and NMOS type transistors are designated by references starting by “TN”.
The read amplifier SA
1
comprises a reference stage RFST, a read stage RDST and a differential stage DIFST
1
electrically supplied by a voltage Vcc and receiving a reference voltage Vref delivered by a generator RGEN. The read amplifier SA
1
has an output node SENSEOUT to be linked to a memory cell to be read, and an output node DATAOUT delivering data at 1 (Vcc) or at 0 (ground) depending on the conductivity state of the memory cell.
The generator RGEN comprises for example a transistor TP
0
, the source S of which receives the voltage Vcc, the drain D of which is connected to a current generator IGEN, and the gate G of which is linked to the drain D. The transistor TP
0
is passed through by a current Iref imposed by the current generator IGEN, and the voltage Vref is sampled at its gate G.
The reference stage RFST comprises two transistors TP
1
, TN
1
in series. The transistor TP
1
receives the voltage Vcc at its source, the signal Vref at its gate, and its drain is connected to the drain of the transistor TN
1
, the source of which is linked to ground.
The read stage RDST comprises two transistors TP
2
, TN
2
in series. The transistor TP
2
receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN
2
. The source of the transistor TN
2
is connected to the gate of the transistor TN
1
and forms the output SENSEOUT of the read amplifier, at which a voltage V
SENSE
is found.
The differential output stage DIFST
1
comprises a first branch comprising two transistors TP
3
, TN
3
in series and a second branch comprising two transistors TP
4
, TN
4
in series. The transistor TP
3
receives the voltage Vcc at its source, a voltage V
MAT
sampled from the drain of the transistor TP
2
(also the drain of the transistor TN
2
) at its gate, and its drain is connected to the drain of the transistor TN
3
, the source of which is linked to ground. The transistor TP
4
receives the voltage Vcc at its source, the voltage Vref at its gate, and its drain is connected to the drain of the transistor TN
4
, the source of which is linked to ground. The transistor TN
4
has its drain connected to its gate, and its gate is connected to the gate of the transistor TN
3
. The output DATAOUT is formed by the mid-point of the transistors TP
3
, TN
3
, i.e., the drain of the transistor TP
3
and the drain of the transistor TN
3
.
The read amplifier also comprises a precharge transistor TP
5
, the source of which receives the voltage Vcc, and the drain of which is linked to the drain of the transistor TN
2
. The gate of the transistor TP
5
is driven by a voltage Vp. The transistors TP
0
, TP
1
, TP
2
, TP
3
, TP
4
are preferably identical and the transistors TN
1
, TN
2
, TN
3
, TN
4
are also identical (same gate aspect ratio).
As an example of an application, it will now be assumed that the output SENSEOUT is linked to a memory cell MCELL through a column decoder COLDEC and a bit line BLj of a memory array MA. The memory cell comprises a floating-gate transistor FGT receiving a read voltage Vread at its gate and the conductivity state of which depends on its programmed or erased state.
The reading of the memory cell MCELL is preceded by a precharge phase during which the voltage Vp is taken to 0. The transistor TP
5
is in a transmission state and a precharge current is delivered by the output SENSEOUT. This precharge current charges stray capacitances of the bit line BLj and brings the voltage V
SENSE
to a determined value, in the order of Vtn (threshold voltage of an NMOS transistor). The transistor TP
5
allows the precharge time to be accelerated and, as a result, the global read time, as the transistor TP
2
operates as a current generator and is not capable of delivering a high precharge current. During the precharge phase, the voltage V
MAT
is equal to Vcc and the transistor TP
3
is blocked. The transistor TN
4
is passed through by the current Iref present in the generator RGEN based upon a current mirror effect between the transistors TP
4
and TP
0
. The transistor TN
3
is also passed through by the current Iref based upon a current mirror effect with the transistor TN
3
. The output DATAOUT is therefore at 0.
The read step starts when the voltage Vp is taken to Vcc. The transistor TP
5
is then blocked. The output SENSEOUT delivers in the bit line BLj a current Icell, the value of which depends on the conductivity state of the memory cell MCELL. The reference stage RFST is passed through by the current Iref by the current mirror effect between the transistors TP
1
and TP
0
, and the drain of the transistor TP
2
of the read stage RDST also delivers the current Iref by the current mirror effect with the transistor TP
0
. If the current Icell is higher than Iref, the voltage V
MAT
drops, the transistor TP
3
goes into a transmission state and the output DATAOUT goes to 1. If the current Icell is lower than Iref, the voltage V
KAT
stays at the high level and the output DATAOUT stays at 0.
As indicated above, other types of read amplifiers comprise an output stage with an inverting gate. In this case, the differential stage DIFST
1
is replaced by an inverting gate that receives the signal V
MAT
at input and the output of which forms the output DATAOUT of the read amplifier. In this case, the output DATAOUT is at 1 or at 0 depending on whether the signal V
MAT
is lower or higher than a trip point of the inverting gate.
The advantage of a read amplifier with a differential output stage of the type that has just been described is that it is accurate because the value of the output DATAOUT does not depend on the trip point of an inverting gate, and is a function of a comparison of the voltage V
MAT
with the reference voltage Vref. Therefore, the output DATAOUT goes to 0 as soon as V
MAT
becomes lower than Vref.
Another advantage of such a read amplifier is that it has a short read time as the voltage Vref is generally higher than the trip point of an inverting gate, such that the detection of the low level of the voltage V
MAT
is faster with a differential stage than with an inverting gate. However, such a read amplifier has a double drawback. First, the differential output stage is more complex than an output stage with an inverting gate (two MOS transistors being sufficient to obtain an inverting gate). Furthermore, the electrical consumption of the differential output stage is considerable while the electrical consumption of an inverting gate is zero outside commutation periods.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a read amplifier of the type described above in which the differential stage is of a simpler structure and has a lower current consumption.
This object is achieved by providing a read amplifier comprising a read stage linked or intended to be linked to a memory cell that is to be read, a reference stage that is pa
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Nguyen Tan T.
STMicroelectronics SA
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