Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-04-27
2004-01-06
Nguyen, Cuong Quang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06674120
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device which has a planarly dispersed charge storing means (for example, in a MONOS type or an MNOS type, charge traps in a nitride film, charge traps near the interface between a top insulating film and the nitride film, small particle conductors, etc.) in a gate insulating film between a channel forming region and a gate electrode in a memory transistor and is operated to electrically inject a charge (electrons or holes) into the charge storing means to store the same therein and to extract the same therefrom and a method of operating (writing or erasing) the device.
2. Description of the Related Art
In an information society, or high-speed, broadband network society, there is a great demand for large capacity file memories and memories for audio and video applications. Currently, in large capacity memory systems for storage of 1 GB (gigabytes) of data or more, use is made of disk memory systems employing disk storage media such as hard disks and optical disks. In recent years, studies have been actively performed trying to replace the disk media with nonvolatile semiconductor memories in this large market. Furthermore, mobile information terminals, which are capable of connecting to networks and expected to offer a large market in the future, are demanding removable storage media of small size and high reliability, and the nonvolatile semiconductor memory is the first candidate.
Although nonvolatile semiconductor memories suit the trend of small sized and light weighted hardware, presently, their storage capacities are still not sufficient, and semiconductor memories (flash memories) of capacities above 1 GB (gigabytes) and capable of erasure at one time have not been realized, yet. In addition to insufficient storage capacity, the reduction of cost per bit for the nonvolatile semiconductor memories is still not adequate compared with disk memories. In order to solve these problems, it is important to increase the integration degree of the nonvolatile semiconductor memories.
Along with the spread of broadband information networks, write speeds equivalent to the transmission rates of networks (for example, a carrier frequency of 100 MHZ) are being demanded even for nonvolatile semiconductor memories. This is because of the anticipation of development of information delivery employing a high-speed network in the near future. To realize high-speed downloads from networks, even nonvolatile semiconductor memories require write speed improvements of one or more orders of magnitude higher than the write speed of conventional FG-NAND type flash memories at 200 &mgr;s.
As nonvolatile semiconductor memories, in addition to the floating gate (FG) types wherein the charge storing means (floating gate) for holding the charge is planarly formed, there are known MONOS (metal-oxide-nitride-oxide semiconductor) types wherein the charge storing means are planarly dispersed.
In an MONOS type nonvolatile semiconductor memory, since the carrier traps in the nitride film [Si
x
N
y
(0<x<1, 0<y<1)] or on the interface between the top oxide film and the nitride film, which are the main charge-retaining bodies, are spatially (that is, in the planar direction and thickness direction) dispersed, the charge retention characteristic depends on not only the thickness of a tunnel insulating film (bottom insulating film), but also on the energy and spatial distribution of the charges captured by the carrier traps in the Si
x
N
y
film.
When a leakage current path is locally generated in the tunnel insulating film, in an FG type, a large amount of charge easily leaks out through the leakage path and the charge retention characteristic declines. On the other hand, in an MONOS type, since the charge storing means are spatially dispersed, only the charges near the leakage path will locally leak from it, therefore the charge retention characteristic of the entire memory device will not decline much. As a result, in a MONOS type, the disadvantage of the degradation of the charge retention characteristic due to the reduction in thickness of the tunnel insulating film is not so serious as in an FG type.
In addition, in order to realize a high-speed and high capacity nonvolatile semiconductor memory, scaling of its gate length is indispensable, and for this, scaling of the thickness of a tunnel insulating film is required. In an FG type, due to the degradation of the above charge retaining characteristics, scaling of the thickness of a tunnel insulating film is difficult, making a simple gate length scaling difficult. In contrast, in a MONOS type, the thickness of a tunnel insulating film can be made thin, and the gate length can be further miniaturized by that extent easily. That is, a MONOS type is superior to an FG type in scaling of the tunnel insulating film in a miniaturized memory transistor with an extremely small gate length.
To realize a miniaturized memory cell in a MONOS type nonvolatile semiconductor memory, it is important to improve the disturbance characteristic. Therefore, it is necessary to set the tunnel insulating film thicker than the normal thickness of 1.6 nm to 2.0 nm. When the tunnel insulating film is formed relatively thick, the write speed is in the range of 0.1 to 10 ms, which is still not sufficient.
In other words, in a conventional MONOS type nonvolatile semiconductor memory etc., to fully satisfy the requirements of reliability (for example, data retention, read disturbance, data rewrite, etc.), the write speed is limited to 100 &mgr;s.
A high speed is possible if the write speed alone is considered, but sufficiently high reliability and low voltage cannot be achieved. For example, a source-side injection type MONOS transistor has been reported wherein the channel hot electrons (CHE) are injected from the source side (IEEE Electron Device Letter, 19, 1998, p. 153). In this source-side injection type MONOS transistor, in addition to the high operation voltages of 12V for write operations and 14V for erasure operations, the read disturbance, data rewrite, and other facets of reliability are not sufficient.
On the other hand, taking note of the fact that it is possible to inject a charge into part of the dispersed charge traps area by the conventional CHE injection method, recently, it has been reported that by independently writing binary data into the source and drain side of a charge storing means, it is possible to record 2 bits of data in one memory cell. For example, Extended Abstract of the 1999 International Conference on Solid State Devices and Materials, Tokyo, 1999, pp. 522-523, considers that by changing the direction of the voltage applied between the source and drain to write 2 bits of data by injecting CHE and, when reading data, applying a specified voltage with a direction reversed to that for writing, i.e., the so-called “reverse read” method, correct reading of the 2 bits of data is possible even if the write time is short and the amount of the stored charge is small. Erasure is achieved by injecting holes by using a hand-to-hand tunnel current.
By using this technique, it becomes possible to increase the write speed and largely reduce the cost per bit.
However, in a CHE injection type MONOS type nonvolatile semiconductor memory of the related art, since electrons are accelerated in the channel to produce high energy electrons (hot electrons), it is necessary to apply a voltage larger than the 3.2 eV energy barrier of the oxide film, in practice a voltage of about 4.5V, between the source and drain. It is difficult to decrease this source-drain voltage. As a result, in a write operation, the punch-through effect becomes a restriction and good scaling of the gate length is difficult.
In addition, a write current of a few hundred &mgr;A is needed, and as a result, there is another problem that it is impossible to write in parallel a large number of memory cells simultaneously.
Moreover, by a CHE injection method, because the
Kananen Ronald P.
Nguyen Cuong Quang
Rader & Fishman & Grauer, PLLC
Sony Corporation
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