Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-12-18
2004-03-02
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S118000, C714S718000
Reexamination Certificate
active
06701461
ABSTRACT:
TECHNICAL FIELD
The present invention in general relates to a method and apparatus for testing a cache. More particularly, this invention relates to a method and apparatus for testing the cache by using a test command row composed of memory access commands using the cache.
BACKGROUND ART
In the majority of information processing apparatuses manufactured recently, a high speed buffer memory called cache is used in order to enhance the operating speed (to obtain high speed of main memory access). Accordingly, to obtain an information processing apparatus having an excellent performance, it is particularly important to verify that the designed or manufactured cache can operate normally.
Various testing methods are known for verifying the cache. One of such methods is a test called the random command test. An outline of the conventional random command test is explained with reference to FIG.
18
.
In the conventional random command test, first of all, pseudo-random numbers are sequentially generated by a random number generating process. Then, by a random command processing, memory access commands having random operands are created with the help of the generated pseudo-random numbers, and the created memory access commands are given to an apparatus to be tested. This apparatus has the cache.
In the conventional random command test, thus, it is designed to verify the cache by creating memory access commands to be accessed randomly by the blocks for composing the cache. In other words, the conventional random command test is a test expecting generation of actions to be verified (for example, replacement sequence) by repetition of random memory access (a test not guaranteeing generation of actions to be verified).
Besides, since the created random command row is redundant, a same action may be repeated plural times in this test. It is hence practically impossible to verify sufficiently the cache with a great number of entries (number of sets) or number of weights applied in the recent information processing apparatus by employing the conventional random command test.
In the light of such background, it is an object of the invention to present a cache testing apparatus and a cache testing method capable of testing the cache in such manner as to access each block for composing the cache without duplication, while maintaining the random performance of memory access.
DISCLOSURE OF THE INVENTION
A cache testing apparatus of the present invention comprises a cache registration table composed of a plurality of blocks corresponding to each one of a plurality of cache entries, with each block assigned with an address registration region for storing an access address of data stored in a corresponding entry, and a flag region for storing information showing validity of test command corresponding to the entry, command creating means for creating memory access commands including information of cache entry, first registering means for registering the access address of the memory access command in the address registration region when the information in the flag region of the block corresponding to the entry indicated by the memory access command created by the command creating means shows an invalid state, and changing the information in the flag region to the information showing validity, and second registering means for selecting a block having a flag region showing an invalid state when the information in the flag region of the block corresponding to the entry indicated by the memory access command shows a valid state, changing the cache entry included in this address to a cache entry corresponding to the selected block, registering the access address information of the memory access command in the address registration region of the selected block, and changing the information in the flag region of the selected block to information showing validity.
According to the above invention, individual blocks of the cache can be verified (initialized) without duplication. Hence, by using this cache testing apparatus, the cache can be verified at high speed and securely.
The cache testing apparatus of the present invention further comprises invalidating means for changing the information in the flag region of each block of the cache registration table to information showing invalidity, first re-registering means for changing the access address of the memory access command to the access address in the address registration region of the block when the flag region of the block corresponding to the cache entry indicated by the memory access command created by the command creating means shows an invalid region, and also changing the information in the flag region to information showing validity, and second re-registering means for selecting the block having a flag region showing an invalid state when the flag region showing invalid state is not present in the block corresponding to the cache entry indicated by the memory access command created by the command creating means, changing the access address of the memory access command to an access address in the address registration region of the selected block, and changing the information in the flag region of the selected block to information showing validity.
According to the above invention, the action in the event of cache hit of the cache can be verified without duplication. Hence, by using this cache testing apparatus, the cache can be verified at high speed and securely.
In the cache testing apparatus of the present invention, each entry of the cache is composed of a plurality of ways, and each block in the cache registration table is assigned, in each way, with address registration region, flag region, and rank information region showing priority rank of ways, and the invalidating means changes the information in the flag region of the way other than the way of the highest priority rank of each block to information showing invalidity.
According to the above invention, of the actions in the event of cache hit of the cache having a plurality of ways, the action in the event of change of the priority rank can be verified in each block without duplication. Hence, by using this cache testing apparatus, the cache having a plurality of ways can be verified at high speed and securely.
The cache testing apparatus of the present invention further comprises comparing means for comparing the information about the access address of the memory access command created by the command creating means and the address information in the address registration region of a specified block, and address reproducing means for creating address information different from the address registration region when there is the address registration region for storing the address information coinciding with the address information of the memory access command in the block, in which the first and second registering means are the means for changing the address information of the block and memory access command to the address information created by the command reproducing means.
According to the above invention, the action of cache error can be verified in each block without duplication in individual blocks of the cache. Hence, by using this cache testing apparatus, the cache can be verified at high speed and securely.
A cache testing method of the present invention is a cache testing method for testing the cache by using a test command row composed of memory access command using the cache, comprising a step of creating a memory access command including information of cache entry, a step of judging whether the test command using the cache entry indicated by the memory access command is registered or not, a step of registering the memory access command as the test command using the cache entry when test command for the entry is not registered, and a step of selecting other cache entry in which test command is not registered when test command using the entry is registered, changing the cache entry indicated by the memory access command to the selected cache entry, and registering the memory access
Beausoliel Robert
Fujitsu Limited
McCarthy Christopher S
LandOfFree
Method and apparatus for testing a cache does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for testing a cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for testing a cache will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3211360