Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-22
2004-03-16
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S653000, C257S654000
Reexamination Certificate
active
06707105
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a pn junction, and more particularly, a semiconductor device and a resistor having a structure where an insulative isolator is provided on a semiconductor film disposed on an insulative substrate on the opposite side to the substrate without making contact with the substrate.
2. Description of the Background Art
Proposals for a so-called SOI (Silicon On Insulator) structure have been made conventionally.
FIG. 62
is a sectional view exemplifying a structure of a CMOS (Complementary Metal Oxide Semiconductor) transistor
200
having the SOI structure. A P
−
type semiconductor layer
20
is provided on an insulator
9
, and an insulative isolator
40
is provided separately from the insulator
9
on a surface of the semiconductor layer
20
on the far side from the insulator
9
. Such an isolator that is separated from the insulator and provided on the surface of the semiconductor film disposed on the insulator for isolating the surface of the semiconductor layer is hereinafter tentatively referred to as “partial isolator”.
N
+
type source/drain layers
21
and
22
are provided in the semiconductor layer
20
. These source/drain layers and a gate electrode
23
provided on the semiconductor layer
20
with a gate insulating film interposed therebetween constitute an NMOS transistor
2
. Such an NMOS transistor having the SOI structure including the partial isolator is disclosed in “Bulk-Layout-Compatible 0.18 &mgr;m SOI-CMOS Technology Using Body-Fixed Partial Trench Isolation (PTI)” (Y. Hirano et al., 1999 IEEE International SOI Conference, October 1999, pp.131-132), for example.
An N
−
type semiconductor layer
10
is further provided on the insulator
9
. P
+
type source/drain layers
11
and
12
provided in the semiconductor layer
10
and a gate electrode
13
provided on the semiconductor layer
10
with a gate insulating film interposed therebetween constitute a PMOS transistor
1
.
The source/drain layer
22
extends through the semiconductor layer
20
, and the source/drain layer
12
extends through the semiconductor layer
10
in the thickness direction, respectively, to divide the respective semiconductor layers
10
and
20
in a sectional view. There is a semiconductor layer
20
t
being a part of the semiconductor layer
20
and a semiconductor layer
10
t
being a part of the semiconductor layer
10
between the source/drain layers
12
and
22
. The semiconductor layers
20
t
and
10
t
are adjacent to each other to form a pn junction J
1
under the partial isolator
40
, that is, between the partial isolator and the insulator
9
. The pn junction J
1
is positioned in the above-described manner when, for example, the pn junction J
1
is formed at the stage of forming the semiconductor layers
10
and
20
before forming the partial isolator
40
and the partial isolator
40
is then formed on a boundary between the semiconductor layers
10
and
20
.
In this way, semiconductor layers of conductivity types different from each other, i.e., p and n type semiconductor layers are formed as a semiconductor film having the SOI structure in a general LSI (Large Scale Integrated Circuit), and a MOS transistor and a bipolar transistor are formed using these semiconductor layers.
However, it is observed in the structure shown in
FIG. 62
that the pn junction J
1
positioned under the partial isolator
40
results in occurrence of an abnormal leakage current at the pn junction J
1
.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises: a substrate at least having an insulative surface; a semiconductor film provided on the surface of the substrate comprising a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type having an impurity concentration lower than that of the first semiconductor layer, a third semiconductor layer of a second conductivity type opposite to the first conductivity type and a fourth semiconductor layer of the second conductivity type having an impurity concentration lower than that of the third semiconductor layer; and an insulative isolator formed on a surface of the semiconductor film on the far side from the substrate, separately from the surface of the substrate. In the semiconductor device, the second and fourth semiconductor layers form a pn junction extending in the thickness direction of the semiconductor film, and a maximum value of a distance between the pn junction and a boundary between the isolator and the semiconductor film is not more than 2 &mgr;m, when a direction from the boundary to the isolator along the surface of the substrate is taken as a positive direction.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the pn junction has a portion separated from the isolator.
According to a third aspect of present invention, in the semiconductor device of the second aspect, the portion of the pn junction separated from the isolator forms a semiconductor element.
According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, the first, second, fourth and third semiconductor layers are adjacent to each other in this order, and the first and third semiconductor layers function as a contact with respect to the pn junction.
According to a fifth aspect of the present invention, in the semiconductor device of the second aspect, the first, fourth, second and third semiconductor layers are adjacent to each other in this order, and the first and second semiconductor layers function as source/drain layers of MOS transistors having conductivity types different from each other, respectively.
According to a sixth aspect of the present invention, the semiconductor device of the second aspect further comprises a cover having an insulative surface in contact with the portion of the pn junction separated from the isolator.
According to a seventh aspect of the present invention, the semiconductor device of the fifth aspect further comprises a cover having an insulative surface in contact with the portion of the pn junction separated from the isolator.
According to an eighth aspect of the present invention, in the semiconductor device of the second aspect, the second semiconductor layer is provided in the fourth semiconductor layer, the first semiconductor layer includes a pair of first semiconductor layers being formed in the second semiconductor layer, and the pair of first semiconductor layers function as a contact with respect to the second semiconductor layer.
According to a ninth aspect of the present invention, a semiconductor device comprises: a substrate at least having an insulative surface; a semiconductor film provided on the surface of the substrate, having at least one pn junction extending in a thickness direction of the substrate, the at least one pn junction including a pn junction which is applied with voltage; and a metallic compound layer selectively formed on the semiconductor film, being a compound of the semiconductor film and metal. In the semiconductor device, a maximum value of a distance between at least the pn junction which is applied with voltage and a boundary between the metallic compound layer and the semiconductor film is not more than 2 &mgr;m, when a direction from the boundary to the semiconductor film along the surface of the substrate is taken as a positive direction.
According to a tenth aspect of the present invention, the semiconductor device of the ninth aspect further comprises a mask provided on the at least one pn junction for preventing combination of the at least one pn junction with metal of the semiconductor film.
According to an eleventh aspect of the present invention, in the semiconductor device of the tenth aspect, the mask has the same structure as a gate of a MOS transistor to be formed on the semiconductor film in a thickness direction thereof.
A
Ipposhi Takashi
Iwamatsu Toshiaki
Renesas Technology Corp.
Tran Thien
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