Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-11-07
2004-09-21
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S350000, C257S351000, C257S371000
Reexamination Certificate
active
06794717
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having an SOI structure and a method of manufacturing the semiconductor device.
2. Description of the Background Art
Attention has recently been paid to a semiconductor device referred to as an SOI (Silicon-On-Insulator) device to be a high-speed device having low power consumption.
The SOI device is fabricated on an SOI substrate having an SOI structure in which a buried oxide film is interposed between an SOI layer and a silicon substrate. In particular, an SOI device in which an SOI layer to be an upper silicon layer has a small thickness (up to approximately several &mgr;m) is referred to as a thin film SOI device to which attention has been paid and has been expected for application to an LSI for mobile equipment. Conventionally, an SOI element (a (semiconductor) element formed on an SOI layer having an SOI structure) penetrates through Si (silicon) of the SOI layer and is completely isolated through an oxide film for isolation formed over the buried oxide film.
The complete isolation technique is characterized by being latch up free (latch-up is not caused), and resistant to noise and the like because the element is electrically isolated completely from other elements. However, since a transistor is operated in an electrical floating state, there is a problem in that a frequency dependency is caused on a delay time and a floating-body effect, for example, a kink effect in which a hump is generated on a drain current-drain voltage characteristic or the like. In order to suppress the floating-body effect, an isolation oxide film (partial oxide film) is formed in an upper layer portion so as not to come in contact with the buried oxide film and constitutes a partial isolation region together with a part of an SOI layer in a lower layer portion and a body terminal is provided in a body region formed in a region isolated in the partial isolation region. Consequently, a partial isolation technique capable of fixing a substrate potential (body potential) through the SOI layer provided under the partial oxide film is effective. However, there is a problem in that the partial isolation technique does not have the latch up free which is the advantage of the complete isolation technique.
Therefore, there has been developed a partial isolation and complete isolation combination technique having both advantages. In the partial and complete isolation combination technique, trench depths are varied for the partial isolation and complete isolation combination. For this reason, after an oxide film of an isolation oxide film is provided and is then subjected to a CMP processing, dishing is generated in a complete isolation portion having a great trench depth differently from the partial isolation. Accordingly, there is a problem in that the shape of an important isolation edge for the reliability of a gate oxide film is varied between the partial isolation and the complete isolation. In the combination process, moreover, the isolation edge of the complete isolation is lowered so that a threshold voltage of a MOS transistor is locally dropped in an edge portion. Therefore, there is a problem in that a leakage current might be increased.
In only the conventional device, moreover, a distance from the body terminal is varied for each transistor. Therefore, there is a problem in that a body resistance is varied, resulting in a variation in a threshold voltage.
In addition, there is a problem in that a body potential cannot always be fixed with a high stability by the partial isolation technique for fixing the body potential through the SOI layer provided under the partial oxide film.
SUMMARY OF THE INVENTION
A first aspect of the present invention is directed to a semiconductor device including an SOI structure having a semiconductor substrate, a buried insulating layer and an SOI layer, comprising a MOS transistor provided in an element formation region of the SOI layer, and a partial isolation region provided in the SOI layer and serving to isolate the element formation region, the partial isolation region including a partial insulating film provided in an upper layer portion of the SOI layer and a partial insulating film lower semiconductor region to be a part of the SOI layer present in a lower layer portion of the SOI layer, the MOS transistor including source and drain regions of a first conductivity type selectively formed in the SOI layer, respectively, a gate electrode having a gate electrode main part formed through a gate oxide film on a region of the SOI layer between the source and drain regions, and a body region having a body region main part to be a region of a second conductivity type of the SOI layer between the source and drain regions and a body region potential setting portion electrically connected from the body region main part in the element formation region and capable of externally fixing an electric potential.
A second aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the body region potential setting section includes a body region source/drain adjacent portion in a gate width direction adjacently to the source and drain regions and extended in a gate length direction from the body region main part, and the gate electrode further has a gate extension region extended in the gate length direction from an end of the gate electrode main part and formed on a part of the body region source/drain adjacent portion, and serving to electrically block the body region source/drain adjacent portion and the source and drain regions through the gate extension region.
A third aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion includes a first body region source/drain adjacent portion extended in a first direction from the body region main part and a second body region source/drain adjacent portion extended in a second direction opposite to the first direction from the body region main part, and the gate extension region includes a first gate extension region formed on a vicinity of the first body region source/drain adjacent portion and a second gate extension region extended on the second body region source/drain adjacent portion.
A fourth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion includes one body region source/drain adjacent portion, and the gate extension region includes one gate extension region formed on a vicinity of the body region source/drain adjacent portion.
A fifth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the body region source/drain adjacent portion has a high concentration region having a higher impurity concentration of a second conductivity type than that in other regions over a region provided apart from the gate extension region by a predetermined distance.
A sixth aspect of the present invention is directed to the semiconductor device according to the second aspect of the present invention, wherein the gate extension region includes a gate extension region having an impurity concentration of the second conductivity type of 5×10
18
cm
−3
or less.
A seventh aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the body region potential setting portion includes a semiconductor region for body fixation of the second conductivity type formed together with the source region.
An eighth aspect of the present invention is directed to the semiconductor device according to the first aspect of the present invention, wherein the partial isolation film lower semiconductor region has the second conductivity type and is formed in
Ipposhi Takashi
Iwamatsu Toshiaki
Maeda Shigenobu
Matsumoto Takuji
Flynn Nathan J.
Sefer Ahmed N.
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3211061