Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-02-05
2004-04-27
Eckert, George (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S327000, C257S020000, C257S022000, C257S027000, C257S330000, C257S333000, C257S331000, C257S622000, C257S328000, C257S420000
Reexamination Certificate
active
06727551
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a MOS semiconductor device, that is, a semiconductor device having a MOS structure and a method of manufacturing the semiconductor device, and more particularly to an improvement in suppression of a short channel effect of a threshold voltage.
2. Description of the Background Art
First of all, names to be used in this specification will be described. In this specification, a general semiconductor device comprising a structure including a channel region, a pair of source-drain regions interposing the channel region therebetween and a gate electrode opposed to the channel region with an insulating film interposed therebetween, that is, a MOS structure will be hereinafter referred to as a MOS semiconductor device. Typical examples include a MOS transistor, whereas the MOS semiconductor device is not restricted to the MOS transistor. Although a set of a source region and a drain region which interpose a channel region therebetween will be referred to as “a pair of source-drain regions” in this specification, the expression does not always imply that the source region and the drain region have shapes symmetrical with each other.
FIG. 60
is a plan view showing a conventional MOS semiconductor device.
FIGS. 61 and 62
are sectional views taken along the lines K—K and L—L in
FIG. 60
, respectively. A device
150
is constituted as a MOS transistor in which a channel region
95
, a pair of source-drain regions
98
and
99
interposing the channel region
95
therebetween and an isolating film
92
are selectively formed in a main surface of a semiconductor substrate
91
.
The semiconductor substrate
91
is a silicon substrate containing a P-type impurity, and the source-drain regions
98
and
99
contain an N-type impurity. A gate electrode
94
is opposed to an upper surface of the channel region
95
with a gate insulating film
93
interposed therebetween. In other words, the device
150
is constituted as an N-channel type MOS transistor. The gate electrode
94
is formed of polysilicon doped with an N-type impurity.
The gate insulating film
93
is constituted as a silicon oxide film having a thickness of 5 nm, for example. The isolating film
92
is constituted as a silicon oxide film buried in a trench having a depth of approximately 0.3 &mgr;m which is formed to surround the channel region
95
and the source-drain regions
98
and
99
. More specifically, the isolating film
92
constitutes a trench isolation structure. Consequently, the channel region
95
and the source-drain regions
98
and
99
are isolated from other elements (for example, other channel regions and source-drain regions which are not shown) formed on the main surface of the semiconductor substrate
91
.
An upper surface of the isolating film
92
is on a level with upper surfaces of the channel region
95
and the source-drain regions
98
and
99
. For this reason, the gate electrode
94
is opposed to only the upper surface of the channel region
95
. Accordingly, a direction in which an electric field is to be applied from the gate electrode
94
to the channel region
95
is restricted to a vertical direction with respect to the same upper surface.
In the conventional MOS semiconductor device, as described above, the electric field to be applied from the gate electrode
94
to the channel region
95
is restricted to that in the vertical direction with respect to the upper surface. Therefore, there is a problem in that control capabilities of the gate electrode
94
for the channel region
95
are low. Accordingly, as a gate length is reduced with microfabrication of a device, the influence of a drain field is increased so that a threshold is reduced considerably. Thus, a so-called “short channel effect” is caused.
In
FIGS. 61 and 62
, a channel depletion layer
95
a
generated by a gate field and a drain depletion layer
99
a
generated by a drain field come in contact with each other at a gate-drain end (that is, an end of the channel region
95
which is adjacent to the drain region
99
) and a space charge is distributed through so-called “charge share”. These depletion layers are generated when a gate voltage V
G
is higher than zero (0<V
G
) and a drain voltage V
D
is higher than zero (0<V
D
). When the gate length is reduced, a ratio of the drain depletion layer
99
a
to the channel depletion layer
95
a
is increased so that a threshold voltage is largely influenced by the drain voltage. Consequently, the threshold voltage is reduced. This implies the short channel effect.
SUMMARY OF THE INVENTION
In order to solve the above-mentioned problems of the conventional art, it is an object of the present invention to provide a MOS semiconductor device capable of suppressing a short channel effect of a threshold voltage and a method suitable for manufacturing the MOS semiconductor device.
A first aspect of the present invention is directed to a MOS semiconductor device comprising: a semiconductor layer which has a channel region and a pair of source drain regions interposing the channel region therebetween; an isolating film formed on a surface of the semiconductor layer to surround the channel region and the pair of source drain regions; and a gate electrode formed on side surfaces of the channel region that expose to a trench formed on surface portions of the isolating film adjacent to the channel region and on an upper surface of the channel region with a gate insulating film interposed therebetween, thereby covering the upper surface and the at least a part of the side surfaces in the channel region with the gate insulating film interposed therebetween and setting a gate upper surface step defined by a step between an upper surface of a portion covering the channel region and an upper surface of a portion covering the isolating film to be equal to or smaller than a half of a gate length defined by a width of the portion covering the channel region.
Preferably, the trench is formed in such a depth that almost whole side surfaces of the channel region expose, and the gate electrode covers the almost whole side surfaces of the channel region with the gate insulating film interposed therebetween.
A second aspect of the present invention is directed to the MOS semiconductor device according to the first aspect of the present invention, wherein the isolating film has a first isolating film and a second isolating film which are formed of materials different from each other, the first isolating film is provided between the semiconductor layer and the second isolating film so as to cover a bottom surface and a part of side surface of the second isolating film, and the trench is formed on a surface of the first isolating film to expose the first isolating film on its bottom, to expose the channel region on its first side surfaces and to expose the second isolating film on its second side surfaces facing to the first side surfaces.
A third aspect of the present invention is directed to the MOS semiconductor device according to the first aspect of the present invention, wherein the semiconductor layer is an SOI layer of an SOI substrate having a semiconductor substrate, an insulating layer and the SOI layer that are formed one on another in this order.
A fourth aspect of the present invention is directed to the MOS semiconductor device according to the third aspect of the present invention, wherein the trench is formed in such a depth that the insulating layer exposes, and the gate electrode covers almost whole side surfaces of the channel region with the gate insulating film interposed therebetween.
A fifth aspect of the present invention is directed to the MOS semiconductor device according to the fourth aspect of the present invention, wherein the trench is formed to expose at least a part of a bottom surface of the channel region, and the gate electrode covers the at least a part of the bottom surface of the channel region with the gate insulating film interposed therebetween.
A sixth aspect of the pres
Eckert George
Mitsubishi Denki & Kabushiki Kaisha
Nguyen Joseph
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