Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-04
2004-07-27
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S317000
Reexamination Certificate
active
06768158
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nano flash memory element and manufacturing method thereof. In more detail, it relates to a flash memory element having improved overall memory characteristics with a double-gate element being constituted therein for improving the scaling down characteristic of flash memory element.
2. Description of the Related Art
A flash memory is a well-known representative non-volatile memory and is quite useful for various application fields.
A flash memory is widely used for various electronic instruments as well as for memory itself.
In particular, it has been noticed that flash memory is suitable for the recently being developed embedded logic technology which requires a memory having no processing complexity.
A novel type of high-performance, highly-integrated flash memory can produce a large scale of added-value by being linked to a related logic as well as by memory itself, and thus various researches are currently being carried out worldwide on flash memory.
In addition, the capacity increase is urgently required for keeping in step with the functions of current electronic instruments being continuously developed.
Since an element for DRAM memory in the prior art has a comparatively good scaling down characteristic, it can be suited for given specification without any major problem.
On the other hand, as for an element for flash memory whose scaling down characteristic is not so good, a new manufacturing method and/or a new configuration of an element is required.
The main reason for this demand of new configuration is that there exists some limitation in scaling down the size of an element used for flash memory in the prior art.
FIG. 1
a
and
FIG. 1
b
show an example of scaling down a flash memory element in the prior art.
Looking into
FIG. 1
b
comparing with
FIG. 1
a
, it is noticed that the gate height and the junction depth as well as the channel length are reduced, however, the thickness of the tunneling oxide film (
14
) and that of the inter-gates oxide film (
18
) between the floating electrode (
16
) and the control electrode (
20
) are not reduced.
Here, the numeral
10
represents a silicon substrate and the numeral
12
represents a source/drain area.
A conventional metal-oxide semiconductor (MOS) element can easily restrain a short-channel effect by using a thin gate oxide film according to the scaling down, however, a flash memory element can not afford the same performance.
An element constituting a flash memory has a similar configuration to a conventional complementary metal-oxide semiconductor (CMOS) element except having a floating electrode (
16
) for storing electric charges between a control electrode (
20
) and a channel of the element.
A tunneling oxide film (
14
) is constituted under the floating electrode (
16
), and the thickness of a tunneling oxide film (
14
) can not be reduced according to the scaling down.
The reason is that the thickness of a tunneling oxide film (
14
), through which the charges in a channel are tunneling to move into a floating electrode (
16
), can not be reduced less than 7 nm or 8 nm. If the thickness of a tunneling oxide film (
14
) is less than that, the charges stored in a floating electrode (
16
) are leaking back to the channel, and thus the retention characteristic of a memory becomes to be bad.
Researches on silicon-oxide-nitride-oxide-Semiconductor (SONOS) type flash memory element, which has a somewhat modified configuration compared with that of a conventional flash memory element, are currently being carried on. The configuration of SONOS type element is the same as that of
FIG. 1
with the substance of the floating electrode (
16
) being substituted with a silicon nitride film (Si
3
N
4
).
In an SONOS type flash memory element, however, the thickness of oxide-nitride-oxide (ONO) film, which is corresponding to a gate oxide film in a CMOS element, is still thicker than that of the gate oxide film (for example, 2 nm/4 nm/4 nm), and thus the scaling down characteristic is worse than that of CMOS element having the same gate length.
Additionally, there exist traps, in which charges can be stored, in the nitride film corresponding to N in an ONO-structured film, and thus charges are trapped therein during a writing program.
Since the trap density is nonuniform, it requires gate length and width over a certain minimum value, and thus it has a limitation in improving its overall integrity.
SUMMARY OF THE INVENTION
The present invention is proposed to solve the problems of the prior art mentioned above. It is therefore the object of the present invention to provide a flash memory element and manufacturing method thereof, which introduces a new silicon oxide integrated (SOI) double-gate type flash memory element having highly-improved memory characteristics including an improved scaling down characteristic compared with the conventional flash memory element, and thereby fundamentally improves the performance and the integrity of a flash memory element at the same time.
To achieve the object mentioned above, the present invention presents a flash memory element comprising: a first oxide film formed on a surface of a silicon substrate; a fin active area vertically formed on the first oxide film with a narrow width; a gate tunneling oxide film formed on the top and at both sides of the fin active area; a floating electrode formed on the surfaces of the gate tunneling oxide film and the first oxide film for storing electric charges; a inter-gates oxide film formed on the surface of the floating electrode; and a control electrode formed on the surface of the inter-gates oxide film.
To achieve the object mentioned above, the present invention also presents a manufacturing method of a flash memory element comprising: the first process of forming a second oxide film on a silicon film of an SOI type wafer constituted of a silicon substrate, a first oxide film and a silicon film; the second process of forming a fin active area by forming a pattern thereon and etching it thereafter; the third process of forming a gate tunneling oxide film on the top and at both sides of the fin active area; the fourth process of forming a floating electrode on the surfaces of the gate tunneling oxide film and the first and the second oxide films for storing electric charges; the fifth process of forming a inter-gates oxide film on the surface of the floating electrode; and the sixth process of forming a control electrode on the surface of the inter-gates oxide film.
REFERENCES:
patent: 6391752 (2002-05-01), Colinge et al.
patent: 6580124 (2003-06-01), Cleeves et al.
Lee Jong Ho
Shin Hyung Cheol
Harness & Dickey & Pierce P.L.C.
Ho Tu-Tu
Korea Advanced Institute of Science and Technology
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