Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-02-24
2004-03-09
Whitmore, Stacy (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06704916
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and an apparatus for optimizing placement and routing capable of realizing optimum placement and routing (layout) by supplying information on the optimum placement and routing of blocks using design tools (a logic synthesis tool, a timing analysis tool and a net list analysis tool) for LSI design, and to a recording medium for recording a program for optimizing placement and routing.
BACKGROUND OF THE INVENTION
A conventional method of placement and routing (layout) will be described below with reference to the drawings.
FIG. 14
is a flowchart showing a conventional method of placement and routing. In recent years, the HDL (hardware description language) is widely used for the logic design. An LSI designer, who used the HDL, expresses a circuit with a description of RTL (register transfer level) of a high abstractness or a high behavior level. In other words, a net list constituting connection information is produced by use of the HDL described at high level (step S
101
).
After that, the net list produced by the designer is logically synthesized utilizing a logic synthesis tool (step S
102
) and converted into a net list at gate level (step S
103
) The logic synthesis is defined as “a process of realizing a design of low level by mapping the library components automatically from the description of high level”. In the logic synthesis tool, design restraints, such as circuit area, processing speed, and the power consumption, can be set. The process for optimization is performed by combining these restraints. Therefore, when the gate size that can be logically synthesized is small due to the restraints of the logic synthesis tools, then a detailed hierarchical description is required.
Finally, the net list of gate level outputs from the logic synthesis tool is provided as an input to the layout tool, and placement and routing is carried out based on this net list (step S
104
). In the process, clustering is effected based on the hierarchical information of the net list, and wiring is conducted with this state as the optimum placement. The clustering as referred to here is defined as “the process for producing optimized clustering at layout level.”
As described above, in the conventional placement and routing, the net list of gate level produced by the logic synthesis tool is input into the layout tool thereby to carry out the optimum placement and routing. The latest logic synthesis tool has a somewhat increased gate size capable of being logically synthesized due to the improved performance. A gate size of larger scale can thus be described with HDL without the need of detailed hierarchical description on the part of the designer.
However, when the logic synthesis is performed using the logic synthesis tool by the conventional method of placement and routing described above, the net list of outputs is flattened in the block described in HDL collectively. As a result, the hierarchy of the net list after synthesis is lost, and the block subjected to placement and routing is flattened. This leads to the problem that the optimum placement and routing utilizing the layout tool becomes difficult. Specifically, when arranging a collectively synthesized large gate circuit utilizing the layout tool, this gate circuit is arranged only by the connections specified by the net list, followed by routing, with the undesirable result that the wiring becomes longer and the chip area becomes larger than when it is described hierarchically.
SUMMARY OF THE INVENTION
The present invention has been achieved in view of the facts described above. It is the object of this invention to provide a method and an apparatus for optimizing the placement and routing which comprises for producing the optimum clustering information even in the case where a large gate circuit is collectively logically synthesized, in which by optimizing the placement and routing based on the particular clustering information, the wiring length can be shortened and the chip area can be reduced on the one hand, and to provide a recording medium for storing a program for the optimization of the placement and routing on the other hand.
In order to solve the problems and to achieve the object described above, according to a first aspect of the present invention, for optimizing the placement and routing, comprising the steps of producing a net list constituting the circuit connection information in a high-level hardware description language (HDL); executing the logic synthesis of the net list thereby to optimize the logic and output a net list of gate level, determining the clustering based on the logic gap information used for optimizing the logic, and outputting the clustering information representing this determination; and carrying out the placement and routing based on the net list of gate level and the clustering information. Thus, the placement and routing is not carried out by taking only the gate connections into consideration as in the conventional art. In addition, the clusterings in the block are arranged based on the net list of gate level and the clustering information output by the processing of the logic synthesis step, and the gates are arranged in the clusterings and wired.
Further, the step of executing the logic synthesis includes the substeps of extracting the connection information of each clustering in a block that can be synthesized collectively and the connection information of the gates in each of the clusterings from the logic gap information, and based on these information, generating the clustering information. Thus, the connection information of each clustering in a block and the connection information between gates in each clustering are extracted, and based on these information, the clustering information is generated thereby to complement the hierarchical information not described.
Further, the step of placement and routing includes the substeps of arranging the block obtained from the clustering information, subsequently arranging each clustering for each block, further arranging corresponding gates in the clustering, and connecting the wiring between the gates in the state where all the gates are arranged. Thus, the wiring between the gates can be accommodated in the clustering, resulting in a reduced redundant wiring.
According to another aspect of the present invention, a method for optimizing the placement and routing comprises the steps of producing a net list constituting the connection information of the circuits by the hardware description language (HDL) and outputting the net list, analyzing the timing of the net list thereby to output the clustering information including the path delay information between the flip-flops in the net list, and carrying out the placement and routing based on the net list and the clustering information including the path delay information. Thus, the placement and routing is not carried out taking only the gate connections into consideration. In addition, the clusterings are arranged in a block based on the net list described in HDL and the clustering information (including the path delay between the flip-flops) output by the processing of the timing analysis step. Further, the gates are arranged in the clusterings, respectively, and are wired.
Further, the step of timing analysis includes the substeps of determining the clusterings in the descending order of rigidity of the timing restraint based on the path delay information between the flip-flops, and in the case where it is determined that a plurality of clusterings can be included in a block capable of being collectively synthesized, setting a high-level clustering including the plurality of the clusterings, and under this condition, generating the clustering information which expresses all the path delay information and the configuration of the clusterings. Thus, the hierarchical information not described is complemented by generating the clustering information based on the path delay information between the flip-flops.
Further, the step of p
Inoue Yoshio
Nishida Takeshi
Leydig , Voit & Mayer, Ltd.
Whitmore Stacy
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