Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
2002-10-16
2004-04-20
Phung, Anh (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C365S154000
Reexamination Certificate
active
06724650
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device (including a semiconductor memory device) incorporating therein a memory cell array that has a plurality of static memory cells disposed in a row and column array, and more particularly to a semiconductor device in which a unit memory cell is constituted by a four transistor cell having transistors therein that serve as an access transistor (hereinafter, “transistor” is abbreviated as simply “Tr”) and also a load element, eliminating the need for a load resistor (hereinafter, this type of cell is referred to as “a load less 4-Tr cell”).
2. Description of Related Art
In a research and development of a semiconductor device having a static memory cell array therein, various load less 4-Tr cells having no load resistor and constituted by a unit cell consisting of two access Trs and two driver Trs have been proposed to reduce an area of a memory cell array or increase the number of memory cells contained in a unit area of semiconductor device. For instance, Japanese Patent Application Laid-open No. 13(2001)-167573 (hereinafter, referred to as a known example 1) discloses a static semiconductor memory device in which a unit memory cell consists of an access Tr and a driver Tr, both being an n channel field effect Tr (hereinafter, referred to as “NMOS”). Japanese Patent Application Laid-open No. 7(1995)-302847 (hereinafter, referred to as a known example 2), Japanese Patent Application Laid-open No. 12(2000)-124333 (hereinafter, referred to as a known example 3), Japanese Patent Application Laid-open No. 13(2001)-118938 and the like disclose an SRAM (Static Random Access Memory) memory cell consisting of an access Tr and a driver Tr, both being realized respectively by employing a p channel field effect Tr (hereinafter, referred to as “PMOS”) and an NMOS, or a static semiconductor memory device having therein the SRAM memory cell constructed as described above.
FIG. 12
is a circuit diagram illustrating the configurations of a memory cell Ml and a memory cell M
3
of a semiconductor memory device disclosed in the known example 1. Referring to
FIG. 12
, the memory cell M
1
comprises an NMOS
1072
connected between a bit line BL
1
and a node N
105
, and having a gate connected to a word line WL
1
, an NMOS
1074
connected between a bit line /BL
1
and a node N
106
, and having a gate connected to the word line WL
1
, an NMOS
1076
connected between the node N
105
and a ground node, and having a gate connected to the node N
106
, and an NMOS
1078
connected between the node N
106
and the ground node, and having a gate connected to the node N
105
. The NMOSes
1072
,
1074
are referred to as an access Tr and the NMOSes
1076
,
1078
are referred to as a driver Tr.
The memory cell M
3
comprises an NMOS
1082
connected between the bit line BL
1
and a node N
107
, and having a gate connected to a word line WL
2
, an NMOS
1084
connected between the bit line /BL
1
and a node N
108
, and having a gate connected to the word line WL
2
, an NMOS
1086
connected between the node N
107
and the ground node, and having a gate connected to the node N
108
, and an NMOS
1088
connected between the node N
108
and the ground node, and having a gate connected to the node N
107
. The semiconductor memory device of the known example 1 operates as follows: the bit line BL
1
and the bit line /BL
1
are precharged during standby time to set the word lines WL
1
, WL
2
at a voltage level a little bit higher than the ground level; and a current to retain data is stably supplied through the access Tr to a node included in the nodes N
105
to N
108
and maintaining a high level to allow a memory cell to reliably retain data. Note that when a memory cell is accessed, a word line to be selected is set to a high level and a word line unselected is set to the ground level.
FIG. 13
is a circuit diagram illustrating the configurations of an SRAM memory cell disclosed in the known example 2. Referring to
FIG. 13
, the SRAM memory cell comprises a pair of PMOSes
1101
,
1102
as a selection Tr and a pair of NMOSes
1103
,
1104
as a driver Tr whose drains and gates are cross-connected. To the PMOSes
1101
,
1102
is supplied a power supply
1110
via bus Trs
1111
,
1112
and bit lines
1107
,
1108
that specify a Y address (column address). During standby time, a word line
1109
provided for specifying an X address (row address) and connected to the gates of the PMOSes
1101
,
1102
is made to maintain an intermediate voltage level. Thus, an electric power is supplied by the power supply
1110
to a memory cell via the bus Trs
1111
,
1112
and the bit lines
1107
,
1108
, thereby allowing the memory cell to hold data therein. A data read operation is performed as follows. First, the voltage level of a word line connected to an unselected cell is pulled up to disconnect a memory cell from a bit line. Subsequently, the gates of the bus Trs
1111
,
1112
are set to a high level to stop supplying a power to the bit lines
1107
,
1108
. Thereafter, the word line
1109
connected to a selected cell is set to “0” V to make the PMOSes
1101
,
1102
placed into a complete turn-on state, thereby reading data from the selected cell. As described above, a selection Tr is realized by employing the PMOSes
1101
,
1102
and a driver Tr is realized by employing the NMOSes
1103
,
1104
, and during standby time, the PMOSes
1101
,
1102
are made to operate as a pull-up element, thereby permitting a circuit designer to omit a pull-up element and allowing a semiconductor manufacturer to reduce process steps for the manufacture of semiconductor device to a large extent.
Additionally,
FIG. 14
is a circuit diagram illustrating the configuration of a load less 4-Tr CMOS SRAM cell as a unit memory cell included in a semiconductor memory device disclosed in the known example 3. Referring to
FIG. 14
, the SRAM cell comprises PMOSes
1216
,
1217
and NMOSes
1218
,
1219
. The gate, source and drain of the PMOS
1216
are connected respectively to a word line
1230
, a bit line
1231
and a node
1233
, and the gate, source and drain of the PMOS
1217
are connected respectively to the word line
1230
, a bit line
1232
and a node
1234
, and the gate, source and drain of the NMOS
1218
are connected respectively to the node
1234
, the GND and the node
1233
, and the gate, source and drain of the NMOS
1219
are connected respectively to the node
1233
, the GND and the node
1234
. The memory cell operates such that the word line
1230
becomes a high level in a standby state and a low level when the content stored in a memory cell is read therefrom or written thereinto. Furthermore in the semiconductor memory device of the known example 3, a gate length of each of the PMOSes
1216
,
1217
is made larger that that of each of the NMOSes
1218
,
1219
. This construction of gate length suppresses an unfavorable influence of a phenomenon observed when a voltage applied to a drain makes a potential between a source and a channel lowered to thereby lower a threshold voltage, which phenomenon is called DIBL (Drain Induced Barrier Lowering), and makes a change of off-current caused by a potential difference applied between a source and a drain as small as possible, resulting in reduction of a standby current flowing through a memory cell.
A unit memory cell consisting of a load less 4-Tr cell is critically required to have an operating allowance called “static noise margin (hereinafter, referred to as “SNM”) within which a memory cell is able to retain data therein over a longer period of time and operate at a further lower voltage, in addition to general electrical performances of SRAM, i.e., high speed operation, low power consumption specifically in terms of current consumption during standby time. Then, referring to
FIG. 15
, the SNM will briefly be explained below. For example, in a-case where a unit memory cell is configured to have PMOSes
1301
,
1302
as an access Tr shown in FIG.
15
A
NEC Electronics Corporation
Phung Anh
Sughrue & Mion, PLLC
LandOfFree
Semiconductor device having a load less four transistor cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device having a load less four transistor cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device having a load less four transistor cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3208328