Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-11-02
2004-09-14
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S341000
Reexamination Certificate
active
06792571
ABSTRACT:
This application incorporates by reference Taiwanese application Serial No. 89126648, filed on Dec. 13, 2000.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a Viterbi detector for partial response maximum likelihood (PRML) signal processing, and more particularly to a Viterbi detector capable of varying sampling rate and using different parameters for PRML signal processing and capable of being implemented with a single piece of hardware.
2. Description of the Related Art
While various approaches to recording information codes in a recording medium are provided for the improvement of information access density, partial response maximum likelihood (PRML) signal processing, is widely used in recording medium systems, such as optical disk systems.
In the process of transmitting signals, when the channel bandwidth is lower than the bandwidth of the signals transmitted in the channel, inter-symbol interference (ISI) occurs in adjacent bits of the signals in the receiving end. When ISI is serious, it may cause jitter. As the recording density of optical disks increases, jitter caused by ISI becomes more serious, increasing the difficulty in phase-locking. For overcoming this phenomenon, the principle of partial response (PR) channel is applied. In PRML signal processing, the channel response is appropriately equalized in a channel response in terms of a PR polynomial. In this way, ISI is constrained and is in an expectable characteristic, resulting in reduction of jitter when ISI occurring. Thus, the performance of phase-locking is improved. In other words, PRML is potentially a technique of improving the recording density of optical disks.
The PRML signal processing includes the following steps. At first, information codes are read from an optical disk. Then the information codes are inputted to a PR equalizer to perform waveform equalization. Next, detection is performed on the output signal of the PR equalizer by using Viterbi algorithm.
Referring to
FIG. 1
, it illustrates a PRML signal processing apparatus using mark edge (ME) recording method. In
FIG. 1
, modulated information code E is first inputted into a return-to-zero inversion (NRZI) circuit
102
. The modulated information code signal E is then processed by an exclusive-OR gate
104
and a delay element
106
of the NRZI circuit
102
, resulting in an output signal F of the NRZI circuit
102
. After that, the output signal F of the NRZI circuit
102
is written to a recording medium
108
, such as an optical disk. In addition, when the information code signal E has a rising edge, the output signal F of the NRZI circuit
102
has a signal level change, such as a change from zero to one, or from one to zero.
As an example of PRML signal processing, in
FIG. 1
, PR(1, 2, 1) equalization for the output signal F of the NRZI circuit
102
is performed, and the minimum code reversal distance &dgr; is set to two, wherein &dgr;=2 indicates that there are at least two “0”between adjacent “1” in the input signal E of the NRZI circuit
102
.
Referring now to
FIG. 2
, it illustrates the waveforms of the signals in FIG.
1
and corresponding pits on the optical disk, where the signals include the information code signal E, output signal F of the NRZI circuit, reproduction signal G, output signal J′ of the PR equalizer, and output signal Z of the Viterbi detector. In
FIG. 2
, the bit sequence in (a) corresponds to an example the information code signal E while the bit sequence in (b) illustrates the corresponding output signal F of the NRZI circuit
102
. When the information code signal E has a signal level change of rising edge, the signal Z has a signal level change of itself as well; otherwise, the signal level of the signal Z remains unchanged. The signal in (c) is the LD driving signal produced according to the signal F and is used for controlling a LD (not shown in Figures) to perform write operation on the optical disk. Illustration in (d) is to show the pits on the optical disk which the LD performs the write operation on. The signal of (e) is the reproduction signal G corresponding to the data read from the optical disk by using the optical head. The signal of (f) is the output signal J′ of the PR equalizer
110
after the PR(1, 2, 1) process. And the signal of (g) is the output signal Z of the Viterbi detector
112
obtained after processing the signal J′. The PR equalizer
110
and Viterbi detector
112
are called a reproduction signal processing unit
114
.
In addition, the output signal of Viterbi detector
112
is in terms of NRZI signal. When the output signal F of the NRZI circuit
102
has a signal level change of either rising edge or falling edge, the corresponding output signal Z of the Viterbi detector
112
is set to one; otherwise, it is set to zero.
In
FIG. 2
, when the signal F is in a 1 state, the LD driving signal is in the high level and a pit is correspondingly produced on the optical disk.
The reproduction signal processing unit
114
is used for generating the output signal Z of the Viterbi detector
112
by using the reproduction signal G, where the signal Z is theoretically identical to the information code signal E.
The PR equalizer
110
is employed to perform PR(1, 2, 1) equalization. The characteristic of PR(1, 2, 1) equalization is:
J′
(
t
)=0.25
G
(
t−
1)+0.5
G
(
t
)+0.25
G
(
t+
1),
Where J′(t) denotes the value of output signal J′ of the PR equalizer at time t, G(t−1), G(t), and G(t+1) denote the values of reproduction signal G at times t−1, t, and t+1 respectively.
As shown in
FIG. 2
(f), the signal J′ at each point of time is close to one of four levels {0, 0.25, 0.75, 1} (indicated by four parallel lines). Then, the signal J′ is inputted to the Viterbi detector
112
. Finally, the Viterbi detector
112
produces the output signal Z, which is identical to the information code signal E.
Viterbi detector
112
further stores signal level transition patterns of the output signal J′ of the PR equalizer
110
corresponding to each point of time in the form of a trellis. In addition, the Viterbi detector
112
only outputs binary signal
0
or
1
at each point of time. Moreover, when the PR equalizer's output signal J′ has noise, the Viterbi detector
112
selects the nearest signal level transition pattern and stores the selected transition patterns in Viterbi detector
112
.
Referring to
FIG. 3
, it illustrates a structure of the conventional PR equalizer in FIG.
1
. The PR equalizer
110
includes a plurality of delay units (for example, delay units
302
,
304
, and
306
), a plurality of multipliers (for example, multipliers
308
,
310
,
312
, and
314
), and an adder
316
. The delay units are connected in series and delay respective input signals for one time unit. In this way, the signal G is delayed by the delay units, resulting in signals i
N
, i
N−1
, i
N−2
, . . . , i
1
associated with different delay periods. The signals i
N
, i
N−1
, i
N−2
, . . . , i
1
are then multiplied by coefficients C
1
, C
2
, C
3
, . . . , C
N
respectively, and the products are inputted to the adder
316
. The sum of i
N
C
1
, i
N−1
C
2
, i
N−2
C
3
, . . . , i
1
C
N
is the output of the adder
316
, regarding as the output signal J′ of the PR equalizer
110
, where the values of C
1
, C
2
, C
3
, . . . , C
N
are associated with the parameters of the PR equalization.
Referring to
FIG. 4
, it illustrates the Viterbi detector
112
in
FIG. 1
in block diagram form. The Viterbi detector
112
includes a branch metric calculation circuit
402
, an add-compare-and-select (ACS) circuit
404
and a path memory unit
406
. The branch metric calculation circuit
402
is for receiving the output signal J′ of the PR equalizer
110
and calculating the values B000
1
, B000
2
, B001
1
, B011
1
, B100
1
, B110
1
, B111
1
, and B111
2
, called the branch metrics. The ACS circuit
4
Acer Laboratories Inc.
Chase Shelly A
De'cady Albert
Rabin & Berdo P.C.
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