Nonvolatile memory

Details Nonvolatile memory Nonvolatile memory

2002-03-13

2004-01-06

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C365S145000

Reexamination Certificate

active

06674109

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a non-volatile memory, particularly to an MFSFET (Metal-Ferroelectrics-Semiconductor-Field Effect Transistor) type memory.
BACKGROUND OF THE INVENTION
Ferroelectrics researched now is divided largely in two. One is a type detecting reversion charge quantity of a ferroelectric capacitor and is constructed by a ferroelectric capacitor and a selecting transistor.
The other one is a memory detecting resistance change of a semiconductor caused by spontaneous polarization of ferroelectrics. The typical one of this type is MFSFET. This is an MIS structure using ferroelectrics at a gate insulation film. In this structure, it is needed to form directly ferroelectrics on a surface of a semiconductor, and it is very difficult to produce a memory element of good quality because boundary control of ferroelectrics and semiconductor is difficult. Although a memory structure providing a buffer layer at boundary of ferroelectrics and semiconductor is the main current now, we have proposed an FET of MFMIS structure set with a metal layer (M) and an insulation layer (I) at boundary of ferroelectrics/semiconductor as a buffer as shown in FIG.
4
. The FET of MFMIS structure is constructed by laminating a gate oxide film
5
, a floating gate
6
, a ferroelectrics
7
, a control gate
8
on a channel domain
4
formed between source drain domains
2
and
3
of a semiconductor substrate
1
in order.
In this structure, the semiconductor substrate
1
is usually grounded, and the ferroelectrics
7
generates polarization inversion by applying positive voltage to the control gate
8
. Even if voltage of the control gate
8
is removed, negative charge generates at a channel forming domain CH by residual polarization of the ferroelectrics
7
. This state is placed with the state of “1”.
Conversely, by applying negative voltage to the control gate
8
, the ferroelectrics
8
generates polarization inversion to reverse direction. Even if voltage of the control gate
8
is removed, positive charge generates at a channel forming domain CH by residual polarization of the ferroelectrics
8
. This state is placed with the state of “0”. Thus, writing data “1” or “0” to the FET can be carried out.
Reading the written data is carried out by applying reading voltage V
r
to the control gate. The reading voltage V
r
is set at value between threshold voltage V
th1
in the state “1” and threshold voltage V
th0
in the state “0”. When voltage V
r
is applied to the control gate
8
, whether written data is “1” or “0” can be judged by detecting whether drain current flows or not.
Thus, according to the FET of the MFMIS structure, one memory cell can be constructed with one element, and it becomes possible to carry out non-destructive reading excellently.
However, the FET of such the structure has the following problem. At writing, the FET has a form where a capacitor C
f
(capacitance is C
f
) formed by the ferroelectric film
7
and a capacitor C
ox
(capacitance is C
ox
) formed by the gate oxide film
5
(See FIG.
5
). Therefore, when voltage V is applied between the substrate
1
and the control gate
8
, voltage is divided in V
f
and V
ox
and is expressed by the following expression (1).
V=V
f
+V
ox
C
f
V
f
=C
ox
V
ox
=q
  (1)
q: generated charge quantity of the capacitor Therefore, divided voltage V
f
shown in the following expression is applied to the capacitor C
f
formed by the ferroelectric film
7
.
V
f
=V·C
ox
/(
C
f
+C
ox
)  (2)
On the other hand, it needs to make V
f
high some degree in order to let the ferroelectric film
7
carry out polarization inversion at writing.
Therefore, it needs to make capacitance of the ferroelectric film to capacitance of the gate insulation film small. However, there is a problem that dielectric constant of PZT is about 200 to 1000 for example, so it is considerably higher than dielectric constant 3.9 of silicon oxide film constructing the gate insulation film.
Because of that, it is difficult to make V
f
high in the above expression (1). Therefore, there is a problem that polarization inversion of the ferroelectric film
7
at writing.
In order to solve the problem, it needs to make dielectric constant of the ferroelectric film as small as possible and make film thickness thin. Thus, although it is possible to make the divided voltage V
f
by making film thickness thin, on the other hand, as film thickness becomes thin, leakage current appears between the floating gate and the control gate, and that causes deterioration of memory characteristic.
The invention is carried out in view of the above-mentioned condition, and the object is to design decrease of leakage current and improvement of data holding characteristic of memory characteristic.
DISCLOSURE OF THE INVENTION
The invention is characterized by including FET of MFMIS structure letting metal layer (M) and insulator layer (I) stand at boundary of ferroelectric and semiconductor, and further by letting an insulation barrier layer between a floating gate or a control gate and a ferroelectric layer.
That is, a first memory of the invention is characterized by comprising an FET having MFMIS structure laminating in order a floating gate a ferroelectric layer, and a control gate on surface of a semiconductor substrate between source-drain domains formed on the surface of a semiconductor substrate through a gate insulation film, wherein the insulation barrier layer stands between said floating gate or said control gate and said ferroelectric layer.
According to such the construction, since the insulation barrier layer stands between the floating gate or the control gate and the ferroelectric layer, leakage current between the floating gate and the control gate is decreased and it is possible to obtain good memory characteristic.
The second invention is characterized in that said insulation barrier layer comprises insulation material including composition elements of said ferroelectric film in the nonvolatile memory according to the first invention.
According to such the construction, adding to effect by the above-mentioned first invention, because said insulation barrier layer includes composition elements of said ferroelectric film, diffusion of said elements from said ferroelectric film is prevented at use for long time and diffusion of composition elements from the insulation barrier layer too is prevented so as to design a long life.
In the third invention, said insulation barrier layer is characterized by standing between said ferroelectric layer and said control gate in the nonvolatile memory according to any of the first invention and the second invention.
By such the construction, since the insulation barrier layer may be formed on the upper surface of said ferroelectric film, the construction does not cause disturbing orientation at forming the ferroelectric film.
In the fourth invention, said insulation barrier layer is characterized by standing between said floating gate and said ferroelectric layer in the nonvolatile memory according to any of the first invention and the second invention.
By such the construction, when the insulation barrier layer stands between said floating gate and said ferroelectric layer, it is possible to construct with material narrowing difference of the lattice constant between that of said floating gate and that of said ferroelectric film.
Desirably, the invention is characterized in that said ferroelectric film is constructed with the STN (Sr
2
(Ta
1−x
Nb
x
)
2
O
y
), x: 0<x<1, y: 0<y, and said insulation barrier layer is constructed by tantalum oxide (Ta
2
O
5
) according to any of the first invention and the second invention.
Dielectric constant of the STN is about 40 to 50, and dielectric constant of tantalum oxide is about 25. Therefore, voltage falling of tantalum oxide itself is small, and it is possible to design decrease of leak current without falling largely voltage applied to the ferroelectric film. Furthermore, since said tantalum oxide includ

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