Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2001-11-26
2004-04-06
Kunemund, Robert (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S712000, C438S714000, C438S723000, C438S743000
Reexamination Certificate
active
06716763
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the fabrication of integrated circuit devices and, in particular, to a method for controlling striations and CD loss in the integrated circuit during an etching process.
BACKGROUND OF THE INVENTION
Semiconductor integrated circuits are typically fabricated on a wafer or substrate of a semiconductor material such as, for example, silicon or gallium arsenide. During the fabrication, the wafer is subjected to a sequence of steps, which may include photomasking, material deposition, oxidation, nitridization, ion implantation, diffusion, and etching, among others.
Etching may be achieved by wet etching processes or dry etching processes. Dry etch processes, such as a plasma etch or ion-assisted etch, are known for etching materials for semiconductor fabrication in silicon integrated circuit technology. Plasma etches are largely anisotropic or unidirectional. Plasma etches may be used to create spaces or substantially vertical sidewalls in the integrated circuit layers, to transfer a mask pattern to an underlying layer with little or no undercutting beneath mask segment edges and to create contact paths in insulative layers. Plasma etch processes are especially useful for producing sub-quarter micrometer patterns and geometries.
Semiconductor integrated circuits with high device density require the patterning of closely spaced submicrometer lines in semiconductors materials to form submicron geometries such as small area emitters for bipolar transistors, short gates for field effect transistors and narrow interconnection lines between devices. The formation of such polysilicon, metal or insulator structures typically requires definition of the locations of such structures in a layer of photoresist on a layer of polysilicon or insulator by exposure of the photoresist with light passing through a reticle or photomask containing the desired pattern. After exposure and treatment of the photoresist, the underlying layer of the substrate is plasma etched using the patterned photoresist as a template. The masking material protects designated areas of the substrate from the etch process. Subsequent processing steps are determined according to the type of device to be fabricated.
As advances in photolithographic and processing capabilities progressively increase, the lateral dimensions of features in silicon integrated circuits continue to decrease. Fabrication of reduced device geometries in integrated circuits mandates minute contact holes of submicron size on insulation layers and minimum isolation distance requirements measured in terms of critical dimensions (CD). For example, recent generations of complementary metal-oxide silicon integrated circuits (CMOS) have gate regions with dimensions on the order of 0.25 microns, or even 0.18 microns and less in the near future.
As the integrated circuit manufacture goes to the sub-quarter regime, a challenge to the high aspect ratio is that the deep ultraviolet (DUV) resist needed to pattern the integrated circuit is thinner and more malleable than prior photoresists. Large striations and uncontrolled increases in the size of the contact holes, known as CD losses, are common during the photolithographic process in the sub-quarter micron regime.
During photolithography, problems arise because high resolution submicrometer images in photoresist require shallow depth of focus during exposure, but thick photoresist patterns are required because of the poor etch rate between the photoresist and the underlying semiconductor layer. Additional problems occur because of the uncontrolled bake during the plasma etch processing. During this process, the substrate is exposed to ion and electron bombardment, UV light, X-rays, and scattered radiations. As a consequence, irregular topographies, distorted images and CD loss occurs during the exposure of the photoresist layer as shown in
FIGS. 1-2
. These figures illustrate a typical plasma etch of a silicon substrate
40
having an oxide layer
42
deposited thereon. Contact holes
12
,
14
,
16
are etched into wafer
10
. The contact holes
12
,
14
,
16
have an upper surface
38
and a lower surface
36
. Due, in part, to the thin DUV resist and the uncontrolled bake during the etching process, discontinuities
18
,
20
,
22
,
24
,
26
,
28
,
30
and
46
are formed as shown for contact hole
12
. The discontinuities
18
,
20
,
22
,
24
,
26
,
28
,
30
,
46
occur in the contact hole
12
as a result of the plasma etch attacking the side walls of the contact hole
12
. It should be understood that the shape and number of the discontinuities will vary depending upon the specific etching process parameters as well as the material which is being etched. The discontinuities may form which have a first surface
32
and a second surface
34
in the wall
44
of the contact hole
12
. In addition, contact holes
12
,
14
,
16
are formed in a frusto-conical shape instead of a cylindrical shape when formed in the oxide layer
42
.
When two discontinuities
22
,
46
are formed in adjacent contact holes
12
,
14
and become aligned with one another, the integrated circuit suffers a loss in critical dimension (CD loss). CD loss is a critical component of integrated circuit design, especially in the sub-quarter micron regime. Additionally, when the contact holes
12
,
14
,
16
are formed in a frusto-conical shape instead of the desired cylindrical shape, surface area is sacrificed thereby requiring the contact holes
12
,
14
,
16
to be deeper to effectuate the same contact.
A further problem with the prior plasma etching is that as a result of the irregular contact holes
12
,
14
,
16
, an unwanted and uncontrolled increase in the diameter of the contact holes
12
,
14
,
16
may also result. This increased size also impacts the displacement of the metal atoms that fill the contact holes. Thus, in addition to the loss in critical dimension, electrical contacts may also become unreliable.
Several attempts have been made to solve this problem. It has been suggested that the distorted images can be alleviated by employing a three-layer photoresist technique such as in U.S. Pat. No. 5,242,532 (Cain) or by employing a silylation layer process such as in U.S. Pat. No. 5,312,717 (Sachdev et al.). These solutions, however, require additional time consuming and costly steps in the etching process.
Accordingly, there is a need for improved plasma etching that provides a substantially uniform etch without a reduction in the critical dimension and without striations formed in the sidewalls of the etched portion of the substrate. The improved plasma etching technique should provide a substrate having increased uniformity across the substrate surface, a substantially uniform trench, a substantially uniform profile angle and a smooth sidewall.
SUMMARY OF THE INVENTION
The present invention provides a plasma etching process that reduces the striations and the CD loss between two contact holes in a substrate. The present invention provides an etching process in which the substrate of semiconductor material to be etched is formed with a substantially uniform etch without a reduction in the critical dimension and without striations formed in the sidewalls. The method of the present invention includes exposing a substrate to be etched to a first plasma under low-power, preferably at about radio frequency (RF) 150 W and then subsequently contacting the substrate to a conventional high power etch, preferably at about RF 950 W. Additional advantages of the present invention will be apparent from the detailed description and drawings, which illustrate preferred embodiments of the invention.
REFERENCES:
patent: 5242532 (1993-09-01), Cain
patent: 5242536 (1993-09-01), Schoenborn
patent: 5312717 (1994-05-01), Sachdev et al.
patent: 5612574 (1997-03-01), Summerfelt et al.
patent: 5662770 (1997-09-01), Donohoe
patent: 5710067 (1998-01-01), Foote et al.
patent: 5726499 (1998-03-01), Irinoda
patent: 5843226 (1998-12-01), Zhao et al.
patent: 5843266 (1998-12-01), Greenw
Howard Bradley J.
Li Li
Kunemund Robert
Tran Binh X.
LandOfFree
Method of controlling striations and CD loss in contact... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of controlling striations and CD loss in contact..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of controlling striations and CD loss in contact... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3205989