Semiconductor device including memory unit and semiconductor...

Details Semiconductor device including memory unit and semiconductor... Semiconductor device including memory unit and semiconductor...

2001-03-26

2004-05-25

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S777000, C257S779000, C257S780000, C257S784000, C257S786000, C257S723000, C257S686000

Reexamination Certificate

active

06740981

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including at least one of memory unit and a semiconductor module including at least memory units, and more particularly relates to a semiconductor device has at least one of memory unit which can lay over one after another and a semiconductor module has at least a plurality of memory units which can lay over one after another. Further, the invention relates to a semiconductor device has at least one of memory unit which can lay over to at least one of another memory unit of the same structure and a semiconductor module has at least a plurality of memory units which can lay over to each other and formed the same structure.
2. Description of the Related Art
Semiconductor devices are strongly required to be compact as lap top personal computers (PC), portable terminal equipment (PDA), portable phones or the like have become popular. Especially, semiconductor memories for storing a large amount of information such as a dynamic random access memory (called “DRAM” hereinafter) are being required to have an increased storage capacity.
In the foregoing DRAM, a storage capacity realized by a single semiconductor chip depends upon minute machining precision in a semiconductor manufacturing process. In order to assure a sufficient storage capacity, portable equipment should be provided with a plurality of DRAMs (i.e. a plurality of semiconductor chips). Usually, the plurality of DRAMs are two-dimensionally mounted on the same plane of a printed circuit board such as a mother board, daughter board or the like of the portable equipment.
However, with the foregoing mounting structure, the DRAMs occupy a large space on the printed circuit board, so that it has been very difficult to downsize the portable equipment. In order to overcome such a problem, it has been proposed to three-dimensionally mount DRAMs on a printed circuit board.
Referring to
FIG. 16
of the accompanying drawings, a synchronous DRAM system (called “SDRAM” system hereinafter)
100
comprises: four memory banks
101
to
104
; a clock buffer circuit
110
; a command decoding circuit
111
; a control signal generating circuit
112
; an address buffer circuit
113
; a mode register circuit
114
; a refresh counter circuit
115
; a column counter circuit
116
; a data controlling circuit
117
; and a data output buffer circuit
118
. Each of the memory banks
101
to
104
houses a memory cell array
130
, a column decoding circuit
131
, a row decoding circuit
132
, and a sense amplifier
133
thereon.
A storage capacity of each of the memory banks
101
to
104
is 16-Mbits, so that the SDRAM system
100
has a total storage capacity of 64-Mbits. The memory cell array
130
receives 12-bit row address signals and 8-bit column address signals. There are provided 16 data lines. These values depend upon the storage capacity of the SDRAM system
100
. For instance, an SDRAM system having a storage capacity of 256-Mbits uses 13-bit row address signals and 9-bit column address signals.
The clock buffer circuit
110
receives clock signals CLK and CKE. The command decoding circuit
111
receives not only the clock signal CKE but also a chip selecting signal CS, a row address strobe signal RAS, a column address strobe signal CAS, a write enable signal WE, and an address signal A
10
. The address buffer circuit
113
receives address signals A
10
, A
0
-A
9
and A
11
, and bank selecting signals BS
0
and BS
1
. Further, the data output buffer circuit
118
sends and receives data signals DQ
0
to DQn.
The SDRAM system
100
writes and reads data according to the operation flowchart shown in FIG.
17
.
(1) Bank Active Operation
First of all, the address signals A
0
to A
11
are inputted to the address buffer circuit
113
. The 12-bit row address signals are determined on the basis of the address signals A
0
to A
11
(in step
120
). The row address strobe signal RAS, column address strobe signal CAS, and write enable signal WE are inputted to the command decoding circuit
111
. When the row address strobe signal has a low level “L”, the column address strobe signal CAS has the high level “H”, and the write enable signal WE has a high level “H” (in step
121
), the chip selecting signal CS is then inputted to the command decoding circuit
111
. If the chip selecting signal CS has the low level “L” (in step
122
), the SDRAM system
100
will be selected. In this state, the bank selecting signals BS
0
and BS
1
are inputted to the address buffer circuit
113
(in step
123
). One of the memory banks
101
to
104
is activated in response to the bank selecting signals BS
0
and BS
1
. For instance, it is assumed that the memory bank
101
is activated. Even if the chip selecting signal CS has the high level “H” in this state, no data is written and read since the SDRAM system
100
has not been activated. The row address signal CAS is input to the activated memory bank
101
.
(2) Data Write Operation and Data Read Operation
The activated memory bank
101
receives the 9-bit column address signals CAS in response to the address signals A
0
to A
8
inputted to the address buffer circuit
113
(in step
124
). The command decoding circuit
111
receives the row address strobe signal RAS, column address strobe signal CAS and write enable signal WE. In this state, if the row address signal RAS has the high level “H”, the column address strobe signal CAS has the low level “L”, and the write enable signal WE has the high level “H” (in steps
125
and
126
), in the memory cell array
130
of the activated memory bank
101
, a data stored at a memory cell of an address, which is selected on the basis of the row address signal RAS and the column address signal CAS, is read from the memory cell (in step
127
). The data is outputted as the data signal DQ from the data output buffer circuit
118
. On the other hand, if the write enable signal WE has the low level “L”, in the memory cell array
130
of the activated memory bank
101
, the data is written into the memory cell of the address, which is selected on the basis of the row address signal RAS and the column address signal CAS (in step
128
). The data written into the memory cell is inputted to the data output buffer circuit
118
as the data signal DQ.
The SDRAM system
100
to and from which the data is written and read is activated in response to the chip selecting signals CS.
When the SDRAM system
100
shown in
FIG. 16
is packaged as one semiconductor memory and a plurality of SDRAM systems
100
are simply stacked on a printed circuit board, a terminal for supplying the chip selecting signal (i.e. a chip selecting lead pin) is commonly used for all of the SDRAM systems
100
. An external device can neither activate a particular SDRAM system
100
nor write the data into it or read the data therefrom.
Japanese Patent Laid-open Publications No. Hei 2-290048 and No. Hei 6-342874 disclose the inventions which can overcome the foregoing technical problems.
In Japanese Patent Laid-open Publication No. Hei 2-290048 (called “Reference 1”), packages
131
to
134
of the tape-automated bonding type (called “TAB”) are stacked on the printed circuit board
130
as shown in FIG.
18
. The packages
131
to
134
are respectively provided with outer leads
135
A to
135
D for sending common signals such as an address signal, a power source and so on, and outer leads
136
A to
136
D for sending the chip selecting signal CS to the packages
131
to
134
. The outer leads
136
A to
136
D are branched into a plurality of sections, which are dislocated one by one and are electrically connected to terminals
130
A to
130
D of the printed circuit board
130
via the outer leads
137
A to
137
D. In other words, the chip selecting signal CS can be independently supplied to the packages
131
to
134
via the outer leads
137
A to
137
D.
In the Japanese Patent Laid-open Publication No. Hei 6-342874 (called “Reference 2), the package substrates
141
to
144
are stacked on the printe

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