Simple fault tolerance for memory

Details Simple fault tolerance for memory Simple fault tolerance for memory

2001-01-19

2004-01-13

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S047300, C714S710000, C714S711000

Reexamination Certificate

active

06678836

ABSTRACT:

TECHNICAL FIELD
The present invention relates to fault tolerance for memory such as solid-state memory or other memory that may utilize flat memory space such as some disk drives, and more particularly to remapping of faulty memory addresses.
BACKGROUND
Whether memory be embodied in dedicated chips, be integrated into multi-purpose chips, or even be embodied in a disk drive utilizing flat memory space rather than cylinder/sector addressing, it may have locations that fail over time or are faulty at the time of manufacture. However, the majority of locations in the memory typically remain usable. Thus, methods have been devised to compensate for the faulty locations so that the use of the non-faulty locations may continue.
The conventional methods for fault tolerance include adding dedicated spare rows, columns, chips, modules, etc. that provide storage locations that substitute for the faulty locations. The dedicated spares are wasted unless there is a fault requiring a substitution. Other methods include permuting bits within words stored in the memory. These are complex schemes that do not allow memory components of more than one bit width to be used. Large granularity reconfiguration methods may be used whereby a group of locations containing one or more defective locations are disabled but more than the faulty memory area is left unusable.
Other methods include reconfiguring the faulty location to a predetermined location that is blocked. If access to the predetermined location is ever needed for additional storage, the reconfiguration fails. Methods involving arranging the circuitry of devices so that the faulty locations are avoided have been implemented. However, this is only performed during manufacturing and is inapplicable in the field. Other methods shuffle the address bits or fully permute the data, but these methods are more complex.
Accordingly, there is a need for simple fault tolerance for memory.
SUMMARY
The present invention may be viewed as a method for remapping locations in memory. The method involves generating a remapping value. The remapping value is logically combined with an intended address value to generate a remapped address value. A memory location having the remapped address value is then accessed.
The present invention may also be viewed as a system for remapping locations in memory. The system includes a first logic configured to generate a remapping value. A second logic is also included and is configured to combine the remapping value with an intended address value to generate a remapped address value. The system also includes a memory address input configured to access a memory location having the remapped address value.


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