Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-05-09
2004-03-09
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S597000, C438S687000
Reexamination Certificate
active
06703302
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-140275, filed May 10, 2001; and No. 2001-151918, filed May 22, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to method for manufacturing a semiconductor device, particularly to a method of manufacturing a semiconductor device provided with an interlayer insulating film having a low dielectric constant.
2. Description of the Related Art
In recent years, the wiring layer, which was of a single layer structure in the past, has come to be of a multi-layer structure in accordance with progress in the miniaturization and the operating speed of the semiconductor device. As a matter of fact, a semiconductor device having a metal wiring structure including 5 layers or more has been developed and put into commercial production. However, with progress in the miniaturization of the semiconductor device, the delay in the signal propagation caused by the parasitic capacitance between the adjacent wirings and the wiring resistance forms a serious problem. To be more specific, with employment of a multi-layered wiring structure, the problem that the delay in the signal propagation derived from the multi-layered wiring structure obstructs the high speed operation of the semiconductor device becomes serious.
Various measures have been taken to date for avoiding the delay in the signal propagation accompanying the employment of the multi-layered wiring structure. In general, the delay in the signal propagation can be represented by the product between the parasitic capacitance between the adjacent wirings and the wiring resistance. In order to improve the delay in the signal propagation, it is naturally desirable to lower the parasitic capacitance between the adjacent wirings and to decrease the wiring resistance.
To decrease the wiring resistance, it has been tried to change the main constituting material of the wiring to a material having a lower resistivity. For example, it has been tried to change the conventional aluminum wiring into a copper wiring. In this case, however, it is very difficult to form copper wiring by a dry etching process like the conventional aluminum wiring. Therefore, in the case of using copper wiring, employed is the technology of a buried wiring structure.
Also, to lower the parasitic capacitance between the adjacent wirings, it has been tried to form, for example, an insulating film containing SiOF as a main component by a CVD method in place of the conventional SiO
2
-based insulating film. Further, it has been tried to form a so-called “SOG” (Spin On Glass) film having a relative dielectric constant lower than that of the SiO
2
insulating film or a low dielectric constant insulating film such as an organic resin film by a spin coating method.
In general, the practical lower limit of the relative dielectric constant of the conventional SiO
2
insulating film is said to be about 3.9. On the other hand, it is said that the SiOF insulating film permits lowering the relative dielectric constant to about 3.3. It is said, however, that it is very difficult in view of the stability of the film to lower practically the relative dielectric constant of the SiOF insulating film to a level lower than 3.3. On the other hand, it is said that the relative dielectric constant of the SOG film or a low dielectric constant insulating film such as an organic resin film can be lowered to about 2.0. Such being the situation, vigorous researches are being made in an attempt to develop a technology for forming such an SOG film or a low dielectric constant insulating film.
For example, it is disclosed in Japanese Laid-open Patent Application No. 11-506872 that a low dielectric constant insulating film having excellent characteristics can be formed by coating a semiconductor substrate with a material of an insulating film so as to form a coated film, followed by irradiating the coated film with an electron beam.
BRIEF SUMMARY OF THE INVENTION
A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises:
forming a low dielectric constant insulating film containing Si atoms over a semiconductor substrate;
heating the low dielectric constant insulating film while irradiating the low dielectric constant insulating film with an electron beam; and
exposing the low dielectric constant insulating film during or after the heating to a gas promoting the bond formation of the Si atoms.
A method for manufacturing a semiconductor device according to another embodiment of the present invention comprises:
forming a low dielectric constant insulating film over a semiconductor substrate;
heating the low dielectric constant insulating film under an atmosphere containing an inert gas while irradiating the low dielectric constant insulating film with an electron beam; and
irradiating the low dielectric constant insulating film during or after the heating with positively charged ions.
Further, a method for manufacturing a semiconductor device according to still another embodiment of the present invention comprises:
forming a low dielectric constant insulating film containing an organic component over a semiconductor substrate;
transferring the semiconductor substrate into a process chamber;
heating the low dielectric constant insulating film while irradiating the low dielectric constant insulating film with an electron beam within the process chamber;
transferring the semiconductor substrate out of the process chamber after the heating;
introducing an oxidizing gas into the process chamber; and
applying a high frequency voltage to a region within the process chamber having the oxidizing gas introduced therein so as to generate a plasma and, thus, to clean the process chamber.
REFERENCES:
patent: 5952243 (1999-09-01), Forester et al.
patent: 6177143 (2001-01-01), Treadwell et al.
patent: 6489030 (2002-12-01), Wu et al.
patent: 2002/0131246 (2002-09-01), Hawker et al.
patent: 11-506872 (1999-06-01), None
Miyoko Shimada et al, “High-Performance Low-K Dielectric Using Advanced EB-Cured Process”, Interface 416-417, (Sep. 2001).
Shimada et al.; “Method of Manufacturing Semiconductor Device”, U.S. patent application Serila No. 09/982,003, filed on Oct. 19, 2001.
Copy of U.S. patent application Ser. No. 10/105,432, filed Mar. 26, 2002, to Miyajima et al.
Miyajima Hideshi
Nakata Rempei
Shimada Miyoko
Elms Richard
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Smith Brad
LandOfFree
Method of making a low dielectric insulation layer does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a low dielectric insulation layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a low dielectric insulation layer will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3203035