Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-01-14
2004-07-27
Tran, Minhloan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000, C257S335000, C438S358000
Reexamination Certificate
active
06768173
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to high voltage MOS transistors. More particularly, this invention relates to apparatus and methods for forming an MOS transistor with a substrate implant to achieve various combinations of low threshold voltage, high breakdown voltage, and transistor operation at high voltages without experiencing vertical punch-through.
Many applications for semiconductor devices require transistors that are isolated from the substrate and that can operate at high voltages (e.g., greater than 40 volts). Applying a high voltage to a transistor can cause several problems. For example, a high voltage at the drain can cause vertical punch-through in an NMOS transistor with an P-type substrate and in a PMOS transistor with an N-type substrate. Vertical punch-through can cause unwanted current flow between the drain and the buried layer at high drain voltages.
One previously known high voltage DMOS transistor
10
is shown in FIG.
1
A. DMOS transistor
10
has a grounded body and a high threshold voltage. DMOS transistor
10
includes highly doped N-type (i.e., N+) source region
12
, N+ drain region
14
, P-type body region
16
, gate
15
, N-type drain region
13
of an N-type epitaxial layer, and P-type substrate
17
. N-type drain region
13
is tied electrically to N+ drain region
14
(because both regions are N-type) to form an extension of the drain. Thick oxide layer
18
lies between gate
15
and N-type drain region
13
. This configuration reduces the impact generation rate of carriers by reducing the electric field in the drain at high drain voltages. However, thick oxide layer
18
causes DMOS transistor
10
to have undesirably large device dimensions. Thick oxide layer
18
also increases the drain-to-source resistance (R
DS-ON
) which is also undesirable, because thick oxide
18
encroaches down into N-type drain region
13
. A further disadvantage of transistor
10
is that the N-type doping concentration in N-type drain region
13
is higher near bird's beak
18
A of thick oxide
18
than the N-type doping concentration near the lower boundary
18
B of thick oxide
18
. This effect causes an increased electric field under the gate which is also undesirable.
A further disadvantage of DMOS transistor
10
is that it cannot be used as a pass transistor, particularly a high voltage pass transistor. A pass transistor is a device in which the source and the drain regions are interchangeable and preferably symmetrical. In a pass transistor, the source, drain, and body regions must be isolated from the substrate. Furthermore, in a high voltage pass transistor, the body region cannot be tied electrically to either the source or the drain. Transistor
10
does not meet these criteria, because its source (region
12
) and drain (region
14
and a portion of layer
13
) are not symmetrical, body region
16
is tied electrically to the source, and body region
16
is tied electrically to substrate
17
. Further features of the DMOS transistor with grounded body are described in an article by Parpia et al., entitled “A CMOS Compatible High-Voltage IC Process,” IEEE Transactions on Electron Devices, Vol. 35, No. 10, October 1988, pp. 1687-1694.
Another previously known high voltage DMOS transistor
20
with an isolated body is shown in FIG.
1
B. DMOS transistor
20
includes highly doped N-type (i.e., N+) source region
22
, N+ drain region
27
, P-type body region
24
, gate
21
, thick oxide
25
, P-type epitaxial layer
26
, P-type substrate
29
, N-type well
23
in P-epitaxial layer
26
, and highly doped N+ buried layer
28
. N+ buried layer
28
isolates substrate
29
from body region
24
to prevent current flow between these two regions. However, N+ buried layer
28
is tied electrically to drain region
27
through N-well
23
. Therefore, the output capacitance at the drain is undesirably high because N+ buried layer
28
has a wide area. High output capacitance is undesirable because it slows down the frequency of the transistor's output signal. Furthermore, DMOS transistor
20
cannot be used as a pass transistor, because the source (region
22
) and the drain (including regions
27
and
23
) are not symmetrical, and body region
24
is tied electrically to the source at P+ region
19
. Further features of the DMOS transistor with isolated body are described in an article by Tsui et al., entitled “Integration of Power LDMOS into a Low-Voltage 0.5 &mgr;m BiCMOS Technology,” IEDM Digest, 1992, pp. 27-30.
Yet another previously known high voltage MOS transistor
30
is shown FIG.
1
C. Transistor
30
has high voltage P-type well
35
that forms the body region of the device in N-type epitaxial layer
42
. N-type extension regions
36
and
38
in P-well
35
form extensions of the drain and source regions. Transistor
30
also has highly doped N-type regions
32
and
34
. Regions
32
/
36
and regions
34
/
38
are symmetrical and may be used interchangeably as drain and source regions of transistor
30
. Transistor
30
also has N+ buried layer
40
that is not tied electrically to the drain as shown in FIG.
1
C. In transistor
30
, vertical punch-through between the drain and buried layer
40
can occur when the depletion regions of the drain and N-epitaxial layer
42
merge in P-well
35
at high drain voltages. For example, if regions
32
and
36
form the drain, then vertical punch-through can occur when the depletion region of the N-extension
36
PN junction in P-well
35
meets the depletion region of the N-epitaxial layer
42
PN junction in P-well
35
. The output capacitance of transistor
30
is high during vertical-punch-through because the drain and buried layer
40
become electrically coupled together.
To prevent vertical punch-through in transistor
30
, two parameters may be changed. First, the doping concentration of P-well body
35
may be increased (e.g., 4-5×10
12
cm
−2
) to reduce expansion of the drain and buried layer depletion regions at high voltages. High doping in body region
35
causes the undesirable effects of increasing the threshold voltage of the transistor and reducing the breakdown voltage at the drain-to-body junction. Secondly, the depth of body region
35
and the thickness of epitaxial layer
42
may be increased so that the depletion regions do not merge at high voltages.
Because the drain and epitaxial layer depletion regions at 40 volts are each about 3.3 microns (micrometers) thick for MOSFETs, the thickness of the epitaxial layer must be greater than 6 microns. A vertical NPN bipolar junction transistor (BJT) with a breakdown voltage of 40 volts requires only about 4 microns of epitaxial thickness. In BiCMOS processes a uniform epitaxial layer is used for MOSFETs and BJTs (bipolar junction transistors). Because the MOSFETs must have an epitaxial thickness of at least 6 microns to operate properly, the thickness of all of the devices formed in the same wafer including the BJTs must be at least 6 microns to achieve isolation. A thicker epitaxial layer undesirably reduces f
T
(the frequency at which the current gain goes to unity), causes a higher V
CE-SAT
(collector-emitter saturation voltage), and causes a higher collector resistance for the BJTs.
A further technique for reducing the threshold voltage in high voltage transistors involves using retrograde wells. A retrograde well is a region of doped silicon that has a doping concentration which decreases toward the surface of the well. The retrograde well may be used for the body of the transistor to achieve a reduced threshold voltage.
FIG. 2A
is a graph of the doping concentration along a vertical cross section below the gate oxide of an NMOS device with a retrograde P-type well formed in an N-type epitaxial layer on a P-type substrate with a highly doped N-type buried layer. In
FIG. 2A
, solid lines
44
represent the concentration of P-type dopants, and dotted line
46
represents the concentration of N-type dopants.
FIG. 2B
is a graph of the
Fish & Neave
Linear Technology Corporation
Morris Robert W.
Mullen Jeffrey D.
Tran Minhloan
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