Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-08-17
2004-04-27
Ellis, Kevin L. (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06728838
ABSTRACT:
FIELD OF THE INVENTION
This invention generally relates to microprocessors, and more specifically to improvements in cache memory and access circuits, systems, and methods of making.
BACKGROUND
Microprocessors are general purpose processors which provide high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. A cache architecture is often used to increase the speed of retrieving information from a main memory. A cache memory is a high speed memory that is situated between the processing core of a processing device and the main memory. The main memory is generally much larger than the cache, but also significantly slower. Each time the processing core requests information from the main memory, the cache controller checks the cache memory to determine whether the address being accessed is currently in the cache memory. If so, the information is retrieved from the faster cache memory instead of the slower main memory to service the request. If the information is not in the cache, the main memory is accessed, and the cache memory is updated with the information.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in applications such as mobile telecommunications, but not exclusively, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
To further improve performance of a digital system, two or more processors can be interconnected. For example, a DSP may be interconnected with a general purpose processor in a digital system. The DSP performs numeric intensive signal processing algorithms while the general purpose processor manages overall control flow. The two processors communicate and transfer data for signal processing via shared memory. A direct memory access (DMA) controller is often associated with a processor in order to take over the burden of transferring blocks of data from one memory or peripheral resource to another and to thereby improve the performance of the processor.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. In accordance with a first aspect of the invention, there is provided a digital system having at least one processor, with an associated multi-segment cache memory circuit. Within the cache, a data array is arranged as a plurality of lines each having one or more segments. Each of the segments has a corresponding valid bit within the set of valid bits, each valid bit is operable to indicate validity of the corresponding segment. Block circuitry is connected to the set of valid bits, the block circuitry is operable to invalidate a selected range of lines in response to a directive from the first processor. The block circuitry has a start register and an end register each separately loadable by the processor. The start register is operable to select a beginning line of the range of lines and the end register is operable to select an ending line of the range of lines.
In an embodiment of the invention, the block circuitry can invalidate either a single line or a block of lines in response to an operation command from the processor, depending on whether the end register is loaded or not.
In an embodiment of the invention, a set of dirty bits is provided. Each of the segments has a corresponding dirty bit within the set of dirty bits that is operable to indicate dirty data within the corresponding segment. The block circuitry is operable to clean a single line or a selected range of lines in response to a directive from the first processor.
Another embodiment of the invention is a method of operating a digital system having a processor and a memory cache. The processor executes instructions and causes transaction requests to the cache. Data and/or instructions are loaded into requested locations within the cache in response to the transaction requests. Valid bits are used to indicate within the cache that each requested location holds valid data. A program executing on the processor can select a range of locations within the cache and direct that an operation be performed on the range of locations within the cache. The operation can be a flush, a clean, or a clean and flush, for example.
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Chauvel Gerard
Lasserre Serge
Brady III W. James
Ellis Kevin L.
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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