Electrical computers and digital processing systems: memory – Storage accessing and control – Memory configuring
Reexamination Certificate
1997-09-19
2004-07-13
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Memory configuring
C711S004000, C711S112000, C711S173000, C711S203000
Reexamination Certificate
active
06763445
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally directed to a mass storage device and a method for storing information principally for use with a computer system. More particularly, the invention is directed to a virtual mass storage device which is implemented on multiple physical storage devices.
BACKGROUND OF THE INVENTION
Computer hardware and software is constantly improved in terms of complexity, power and sophistication. Many advanced applications have increased the speed and processing requirements for computer hardware, e.g., some real-time applications such as full motion video playback and capture. Moreover, as computer software has become more complex, program sizes have increased and have required larger and more frequent data transfers between main memory systems (e.g., random access memories and cache memories) and various mass storage devices.
Mass storage devices, e.g., hard disk drives, optical drives, tape backup drives, etc., have also had to increase in size to accommodate larger program sizes and increased software memory and processing requirements.
To accommodate the increases in program sizes and frequencies of access to mass storage devices, a need has existed for increasing the data transfer rates of mass storage devices so that data transfers performed with the devices do not unduly slow down software loading, response and execution times.
Several interface standards have been developed to improve the data transfer rates of mass storage devices. For example, an IDE (intelligent drive electronics) standard has been developed for hard disk drives on PC-compatible personal computers. The controller for an IDE drive is incorporated on the drive instead of on a separate controller card. This arrangement decreases signal lengths and enables many of the low level functions (e.g., moving drive heads to particular tracks on the drive) to be handled directly by the controller.
The drive controller is connected via a dedicated high speed bus that is interfaced to the main memory system of a computer through an IDE interface circuit. In many systems, the IDE interface circuit is simply an extension of the PC bus interface, such as the PCI (peripheral component interconnect) bus used in some PC-compatible computer designs.
Another standard which has been developed is the SCSI (small computer systems interface) standard which has been developed for handling different peripheral components, including mass storage devices, MIDI ports, and other peripherals. Under the SCSI standard, each component includes a dedicated controller and is assigned a unique address for being controlled by a master controller interconnected thereto by a SCSI bus. Specific low level functions for a particular device are typically integrated into the device controller.
Both systems have advantages over many prior designs. Most importantly, they have the advantage of faster data transfer. This is due not only to improvements in hardware performance, but is also due to the incorporation of low level functions into the device controllers. The net result is that the processing requirements of the computer's main processing system are reduced. Data transfer rates across an IDE bus are currently be as high as 16 MByte/s for shorter data transfers, and data transfer rates across an SCSI bus are currently as high as 20 MByte/s, although these transfer rates are continuing to increase. Moreover, both systems allow different peripherals to be controlled according to a standard communication and command protocol, thus decreasing compatibility concerns.
However, with both the IDE and SCSI standards, the data transfer rates obtained across the respective buses are typically limited primarily by physical or mechanical limitations of the particular peripheral devices. For example, on a hard disk drive, the limiting factor on the data transfer rate of the drive is the time required to transfer data between the read/write heads and the physical media, which is often a function of the rotational speed of the physical media and the density of information stored on the media. Thus, while IDE or SCSI controllers may be able to transfer data at the aforementioned rates once information is obtained from the physical media of a device, the transfer rates of larger transfers (i.e., the “sustained data transfer rates”) are constrained by the data transfer rate between the drive heads and the physical media.
Some devices may implement on-board sector or cache buffer memories to improve transfer rates for smaller data transfers. However, sustainable data transfer rates for larger transfers are still typically limited, at best, to about 4-8 MByte/s due to the physical limitations of the particular devices.
Improvements in physical device characteristics typically dictate increasing the mechanical or physical performance of the device, e.g., with a hard disk drive increasing the speed of rotation of the disks or increasing the number of bits of information per track. However, improving the mechanical characteristics of a device often comes at a significant cost in terms of development and manufacturability.
Therefore, a need has arisen for a mass storage device with an increased sustainable data transfer rate while accounting for the inherent physical limitations of the device. In particular, a need exists for increasing the sustainable data transfer rate of a mass storage device in a cost effective manner and with little or no hardware modifications to the device.
SUMMARY OF THE INVENTION
The invention addresses these and other problems associated with the prior art in providing a “virtual” mass storage device which implements multiple physical devices for storing information. The virtual mass storage device is organized into blocks of information which are allocated to different physical devices, thereby enabling the physical devices to operate in parallel and increase the overall transfer rate of the virtual device. By “virtual” mass storage device, what is meant is an implementation within a computer system that appears to the computer system to be a single mass storage device, which may be accessed by the computer system like other mass storage devices. However, in the virtual device, the interface to the multiple physical devices which implement the virtual device is “hidden” from the operating system and the software applications running on the computer system.
Physical mass storage devices typically include physical address spaces for storing data, which are formatted to be accessed via distinct physical addresses. The physical address spaces of many physical devices are arranged into physical sectors, and may be further arranged into physical blocks of physical sectors.
A preferred virtual device may utilize a data manager for handling data transfers with the physical devices. The data manager may define a virtual address space for accessing the data stored on the physical devices. The virtual address space may be accessed via distinct logical addresses, and the data manager may assign or map each logical address to a specific physical address on one of the physical devices. Similar to the physical devices, the logical addresses may be arranged into logical sectors, and further, into logical blocks of logical sectors.
Data transfer requests may be made to a preferred virtual device by requesting specific logical addresses within the virtual address space of the device. A data manager may then assign the logical addresses to physical addresses on the physical devices, and thereby handle the transfer of data with each of the physical devices. Multiple physical devices may, therefore, be accessed through a single virtual device handler.
In preferred virtual devices where ranges of logical addresses are mapped to physical sectors on more than one physical device, overall sustainable data transfer rates may be improved by requesting the physical devices to begin to access data at substantially the same time (which typically occurs at the physically or mechanically limited sustained data transfer rates of th
Anderson Eric D.
Klein Dean A.
Knobbe Martens Olson & Bear LLP
Micro)n Technology, Inc.
Namazi Mehdi
Padmanabhan Mano
LandOfFree
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