Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-01
2004-04-06
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06718531
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for designing integrated circuits. More particularly, the present invention relates to a method for designing integrated circuits using a hierarchical design technique.
2. Description of the Related Art
A hierarchical design technique is widely used for designing integrated circuits. The hierarchical design effectively improves efficiency of the design of the integrate circuits.
A hierarchical layout method is disclosed in Japanese Patent No. 2980316. As shown in
FIG. 1A
, the hierarchical design method begins with floor planning of a top-level hierarchical cell (top-level layer). As a result, macros
101
a
,
101
b
and
101
c
and an interconnecting path
102
are incorporated in the top-level hierarchical cell. The interconnecting path
102
is used for transmitting a signal from the macro
101
a
to the macro
101
c
. The interconnecting path
102
is designed so as to pass through the macro
101
a.
The interconnecting path
102
is composed of interconnections
103
,
104
and a repeater buffer
105
. The repeater buffer
105
reduces a delay taken for a signal to be transmitted from the macro
101
a
to the macro
101
c.
As shown in
FIG. 1B
, the macro level design data (or low-level design data) representative of a layout of macros (or low-level hierarchical cells) is then generated from a top-level design data representative of the layout of the top-level hierarchical cell. In the example shown in
FIG. 1B
, the macro level design data representative of the layout of the macro
101
b
is generated from the top-level design data.
The process of the generation of the macro level design data is described below. At first, virtual terminals
106
b
,
106
c
are generated at intersections of the interconnections
103
,
104
and the boundary of the macro
101
b
, respectively. The interconnection
103
is divided into an interconnection
103
a
and an interconnection
103
b
by the virtual terminal
106
b
. Similarly, the interconnection
104
is divided into an interconnection
104
a
and an interconnection
104
b
by the virtual terminal
106
c
. The information representative of the arrangements of the interconnection
103
a
and the interconnection
104
a
, which are located outside the macro
101
b
, is left in the top-level design data. On the other hand, the information representative of the arrangements of the interconnection
103
b
, the interconnection
104
b
, and the repeater buffer
105
, which are located inside the macro
101
b
, is separated from the top-level design data and embedded into the macro level design data.
Next, the layouts of the interconnections
103
b
,
104
b
are modified to optically determined the layout inside the macro
101
b
on the basis of the macro level design data. The positions of the virtual terminals
106
b
,
106
c
and the repeater buffer
105
are not changed by the modification of the layouts.
In the conventional hierarchical design method, the interconnecting path is determined so as to pass through the macro
101
b
, and the interconnecting path is further embedded in the macro
101
b
when the macro is designed. This prevents the interconnecting path of the top-level hierarchical cell from taking a long way around the macro
101
b
, and thus reduces the delay of the interconnecting path of the top-level hierarchical cell.
However, the conventional hierarchical design method requires a merge of the top-level design data and the macro level design data before a timing analysis, because the typical timing analysis tool does not comply with the timing analysis of the LSIs by the conventional hierarchical design method. The necessity of the merge of the top-level design data and the macro level design data reduces the merit of concurrent layout designs of a plurality of hierarchical levels.
With reference to
FIG. 2
, a typical timing analysis tool requests the provisions of data representative of:
the waveform rounding parameter of an input signal to an input terminal
202
;
the resistance of an interconnection connected to an output terminal
203
from which an output signal is outputted; and
the load capacitance of the output terminal
203
. Here, the waveform rounding parameter implies the time taken for the input signal to rise up from a Low-level to a High level, or to trail from the High level to the Low-level. Typically, the time required for the input signal to rise from 10% of the High level to 90%, or to trail from 90% of the High level to 10% is used for representing the waveform rounding parameter. A delay of the macro is calculated during the timing analysis on the basis of the waveform rounding parameter of the input signal, the resistance of the interconnection connected to the output terminal, and the load capacitance of the output terminal.
The process of calculating a delay of a buffer included in the macro by a typical timing analysis tool is as follows. With reference to
FIG. 3
, let us suppose that the macro
201
includes a buffer
204
and an interconnection
205
connected to an output terminal of the buffer
204
. The typical timing analysis tool calculates a delay T
g
of the buffer
204
by the equation (1):
T
g
=f
1
(
T
rf
, R, C+C
in
), (1)
where f
1
is a predetermined function, T
rf
is the waveform rounding parameter at the input terminal of the buffer
204
, R is the resistance of the interconnection
205
connected to the output terminal of the buffer
204
, C is the capacitance of the interconnection
205
, and C
in
is the capacitance of an input terminal of another cell
206
to which the interconnection
205
is connected.
In addition, the typical timing analysis tool calculates a delay T
w
of the interconnection
205
by the equation (2):
T
w
=f
2
(
R, C+C
in
)+
T
rf′
, (2)
where T
rf′
is the waveform rounding parameter at the input terminal of the cell
206
. The waveform rounding parameter T
rf′
is calculated by the equation (3):
T
rf′
=f
3
(
D, R, C+C
in
), (3)
where D is a driving ability of the buffer
204
for outputting a signal to the interconnection
205
.
With reference to
FIG. 4
, let us consider the case when the timing analysis is performed with respect to the macro
101
b
embedded in a LSI designed by the conventional hierarchical design method.
A delay T taken for a signal to be transmitted from a virtual terminal
106
b
to a virtual terminal
106
c
is given by:
T=T
w1
+T
g1
+T
w2
,
where T
w1
is a delay of the interconnection
103
b
, T
g1
is a delay of the repeater buffer
105
, and T
w2
is a delay of the interconnection
104
b.
From the equation (2), the delay T
w1
is given by:
T
w1
=f
2
(
R
2
, C
2
+C
in1
)+T
rf1
,
where R
2
is the interconnection resistance of the interconnection
103
b
, C
2
is the interconnection capacitance of the interconnection
103
b
, C
in1
is the capacitance of the input terminal of the repeater buffer
105
, and T
rf1
is the waveform rounding parameter at the input terminal of the repeater buffer
105
.
The waveform rounding parameter T
rf1
can not be calculated by using the typical timing analysis tool, because the typical timing analysis tool does not have the function of receiving all parameters required to calculate the waveform rounding parameter T
rf1
. The waveform rounding parameter T
rf1
is given by the equation (3) as follows:
T
rf1
=f
3
(
D
1
, R
1
+R
2
, C
1
+C
2
+C
in1
),
where D
1
is the driving ability of a buffer
101
a
for outputting an input signal to the virtual terminal
106
b
, R
1
is the resistance of the interconnection
103
a
connected to the virtual terminal
106
b
, C
1
is the capacitance of the interconnection
103
a
. The typical timing analysis tool has the function of receiving the waveform rounding parameter of the input terminal to the virtual terminal
106
b
. However, the typical timing analysis tool does not have the function of receiv
Hayes & Soloway P.C.
Levin Naum
NEC Electronics Corporation
Siek Vuthe
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