Method of design for testability, method of design for...

Details Method of design for testability, method of design for... Method of design for testability, method of design for...

2001-02-22

2004-03-16

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06708315

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a design for testability technique for facilitating generation of test input patterns for fault testing of integrated circuits.
One of the conventional methods of design for testability for integrated circuits is a full-scan design method (see “Digital Systems Testing and Testable Design,” Computer Science Press, Chapter 9, pp. 343-395, 1990).
According to the full-scan design, all FFs (flip-flops) in the circuit are replaced with scan FFS, which are connected in the form of a shift register. Since the values of the FFs can be arbitrarily set and read through the shift register during testing, the scan FFs can be regarded as external inputs/outputs (I/Os). Therefore, for the full-scan design circuits, test input patterns achieving a high fault coverage can be easily generated with a combinational test input pattern generation algorithm.
Another example of the conventional methods of design for testability is a partial-scan design method. According to the partial-scan design, a part of the FFs in the circuit is replaced with scan FFs, which are connected in the form of a shift register. The partial scan design can reduce the area overhead, degradation in delay, and power consumption as compared to the full-scan design, but generally requires a sequential test input pattern generation algorithm to generate test input patterns. A method for selecting FFs to be replaced with scan FFs is of importance for a high fault coverage.
A method for selecting FFs to be replaced with scan FFs has been proposed which is capable of generating test input patterns of a partial-scan design circuit with a combinational test input pattern generation algorithm. It is reported that this proposed method can achieve a high fault coverage like the full-scan design (See T. Inoue et al., “An RT level Partial Scan Design Method Based on Combinational ATPG,” TECHNICAL REPORT of IEICE, FTS96-67, February. 1997).
The scan design is a design for testability that replaces the existing FFs with scan FFs and connects them in the form of a shift register. In addition to the scan design, there is a test point insertion technique intended to improve the fault coverage of the circuits. More specifically, test points are inserted into signal lines having poor circuit controllability or observability (the circuit controllability is herein the degree of difficulty in setting “0” or “1” to signal lines within a circuit, and the observability is the degree of difficulty in observing the values of signal lines within a circuit) (see M. Nakao et al., “Accelerated Test Points Selection Method for Scan-Based BIST,” IEEE 1997 Asian Test Symposium, pp. 359-364).
With the progress in semiconductor integration technology, integrated circuits have been increasingly miniaturized, causing a significant increase in the number of FFs included in the integrated circuit. In contrast, the number of external pins of the integrated circuit has been increased only slightly due to the structure of the integrated circuit. Therefore, in the current mainstream full-scan design, a significantly increased number of scan FFs are present in a single scan path, resulting in a significant increase in the number of test input patterns by a tester.
FIG. 41
schematically shows an example of the full-scan circuit. In
FIG. 41
, PI
1
, PI
2
and PI
3
denote external inputs, PO
1
and PO
2
denote external outputs, FF
1
, FF
2
, FF
3
and FF
4
denote scan FFs, SI denotes scan-IN, and SO denotes scan-OUT. CK denotes a clock input, and SE denotes a scan-mode input for switching an operation of the respective scan FFs FF
1
to FF
4
.
FIG. 42
shows a test input pattern generation model of the full-scan circuit of FIG.
41
. In
FIG. 42
, normal data inputs of the scan FFs FF
1
to FF
4
are converted into pseudo external outputs PPO-FF
1
to PPO-FF
4
, and outputs of the scan FFs FF
1
to FF
4
are converted into pseudo external inputs PPI-FF
1
to PPI-FF
4
, respectively, so that the entire circuit is converted into a combinational circuit.
FIG. 43
shows test input patterns generated for the test input pattern generation model of FIG.
42
. In
FIG. 43
, the external inputs are represented by “0” and “1”, and expected values of the external outputs are represented by “H” and “L”. The test input patterns for the test input pattern generation model as shown in
FIG. 43
are herein referred to as “parallel test input patterns”. In
FIG. 43
, two parallel test input patterns V
1
and V
2
are generated, and therefore the number of parallel test input patterns is “2”.
An actually manufactured integrated circuit is a full-scan design circuit rather than the test input pattern generation model. Therefore, the parallel test input patterns as shown in
FIG. 43
cannot directly be used for testing the integrated circuit with a tester. In other words, the parallel test input patterns generated for the test input pattern generation model must be converted into test input patterns of the actual full-scan design circuit.
FIG. 44
shows the parallel test input patterns of
FIG. 43
converted into test input patterns for an actual full-scan design circuit. In
FIG. 44
, “−” indicates that no test input pattern is input, the rising edge of the clock CK indicates that a clock has been input, and “*” indicates that the expected values are not compared.
First, in order to set the values of the pseudo external inputs PPI-FF
1
to PPI-FF
4
of the first parallel test input pattern V
1
, of
FIG. 43
to the scans FFs FF
1
to FF
4
of
FIG. 41
, respectively, the circuit of
FIG. 41
is rendered in a shift mode (SE=1), and the clock CK is input four times with “0”, “1”, “0” and “0” being sequentially set to the scan-IN SI. Thus, “1”, “0”, “1” and “0” are respectively set to the scan FFs FF
1
to FF
4
.
Then, the circuit of
FIG. 41
is rendered in a capture mode (SE=0), and the clock CK is input once, whereby the respective normal data input values are set to the scan FFs FF
1
to FF
4
. In order to read these values from the scan-OUT SO, it is necessary to render the circuit of
FIG. 41
again in the shift mode and to input values from the scan-IN SI.
Then, in order to set the values of the pseudo external inputs PPI-FF
1
to PPI-FF
4
of the second parallel test input pattern V
2
of
FIG. 43
to the scans FFs FF
1
to FF
4
, respectively, the circuit of
FIG. 41
is rendered in the shift mode (SE=1), and the clock CK is input four times with “1”, “0”, “1” and “0” being sequentially set to the scan-IN SI. Thus, “0”, “1”, “0” and “1” are respectively set to the scan FFs FF
1
to FF
4
, as well as the normal data input values that have been set to the respective scan FFs FF
1
to FF
4
in the capture mode are sequentially observed from the scan-OUT SO. In other words, this operation enables observation of the external outputs of the pattern V
1
as well as setting of the external outputs of the pattern V
2
.
Thus, by inputting all parallel test input patterns while repeatedly executing the shift mode and the capture mode, the expected values are compared.
Accordingly, the number of test input patterns by the tester of the scan design circuit can be given by the following equation:
The number of test input patterns by the tester=(the number of parallel test input patterns+1)×the maximum number of scan FFs present in a single scan path+the number of parallel test input patterns.
As can be seen from the above equation, as the number of scan FFs present in a single scan path is significantly increased, the number of test input patterns by the tester is remarkably increased. This means that the test time of an actual integrated circuit is increased, causing increased costs of the integrated circuit.
Moreover, an increased circuit scale requires a decoder circuit and a combinational circuit using a number of input variables to be tested with a large number of test input patterns.
The number of test input patterns by the tester of the partial-scan design circuit is signific

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