Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-10-22
2004-09-28
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S261000, C438S262000, C438S418000, C438S257000, C438S411000, C438S689000, C438S258000, C257S319000, C257S321000, C257S345000, C257S346000, C257S347000
Reexamination Certificate
active
06798015
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device including a memory region and a method of manufacturing thereof. More particularly, the present invention relates to a method of manufacturing a semiconductor device in which a nonvolatile memory device formed in the memory region includes two charge accumulation regions for one word gate.
As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon) memory device is known. In this type of memory device, a gate insulating layer between a channel region and a control gate is formed of a laminate consisting of silicon oxide layers and a silicon nitride layer, and a charge is trapped in the silicon nitride layer.
A device shown in
FIG. 17
is known as the MONOS nonvolatile semiconductor memory device (non-patent document: Y. Hayashi, et al., 2000 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123).
In this MONOS memory cell
100
, a word gale
14
is formed on a semiconductor substrate
10
through a gate insulating layer
12
. A control gate
20
and a control gate
30
in the shape of sidewalls are disposed on each side surface of the word gate
14
. An insulating layer
22
is disposed between the bottom of the control gate
20
and the semiconductor substrate
10
. A side insulating layer
26
is disposed between the side surface of the control gate
20
and the word gate
14
. The insulating layer
22
is disposed between the bottom of the control gate
30
and the semiconductor substrate
10
. The side insulating layer
26
is disposed between the side surface of the control gate
30
and the word gate
14
. Impurity layers
16
and
18
which form either a source region or a drain region are formed in the semiconductor substrate
10
between the control gate
20
and the control gate
30
which face each other in the adjacent memory cells.
As described above, one memory cell
100
includes two MONOS memory elements, one on each side surface of the word gate
14
. The two MONOS memory elements are controlled separately. Therefore, one memory cell
100
is capable of storing two bits of information.
BRIEF SUMMARY OF THE INVENTION
The present invention may provide a semiconductor device which includes a MONOS nonvolatile memory device having two charge accumulation regions and has tolerance to deterioration during data writing/erasing, and a method of manufacturing the same.
According to one aspect of the present invention, there is provided a semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns,
wherein each of the nonvolatile memory devices includes:
a word gate formed over a semiconductor layer with a gate insulating layer interposed in between;
an impurity layer formed in the semiconductor layer to form one of a source region and a drain region; and
control gates in the shape of sidewalls formed along both side surfaces of the word gate,
wherein each of the control gates includes a first control gate and a second control gate adjacent to each other,
wherein a first insulating layer formed of a first silicon oxide film, a silicon nitride film, and a second silicon oxide film is disposed between the first control gate and the semiconductor layer, and a side insulating layer is disposed between the first control gate and the word gate;
wherein a second insulating layer formed of a silicon oxide film is disposed between the second control gate and the semiconductor layer, and
wherein the thickness of the second insulating layer is smaller than the thickness of the first insulating layer.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device having a memory region in which a memory cell array is formed of non-volatile memory devices arranged in a matrix of a plurality of rows and columns, the method comprising the steps of:
(a) forming a gate insulating layer over a semiconductor layer,
(b) forming a first conductive layer over the gate insulating layer,
(c) forming a stopper layer over the first conductive layer,
(d) patterning the stopper layer and the first conductive layer to form a stack of layers formed of the stopper layer and the first conductive layer,
(e) forming a first insulating layer formed of a first silicon: oxide film, a silicon nitride film, and a second silicon oxide film over the entire surface of the memory region,
(f) forming a second conductive layer over the first insulating layer and anisotropically etching the second conductive layer to form a first control gate in the shape of a sidewall along both side surfaces of the first conductive layer over the semiconductor layer with the first insulating layer interposed in between,
(g) removing the silicon nitride film and the second silicon oxide film of the first insulating layer by using the first control gate as a mask to form a second insulating layer,
(h) forming a third conductive layer over the entire surface of the memory region, and anisotropically etching the third conductive layer to form a second control gate at a location adjacent to the first control gate and over the semiconductor layer with the second insulating layer interposed in between,
(i) forming an impurity layer in the semiconductor layer to form one of a source region and a drain region,
(j) forming a third insulating layer over the entire surface of the memory region and removing the third insulating layer so as to expose the stopper layer, and
(k) removing the stopper layer, forming a fourth conductive layer, and then patterning the fourth conductive layer to form a word line.
REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2002-07-01), Ebina et al.
patent: 6518124 (2003-02-01), Ebina et al.
patent: 6627491 (2003-09-01), Ebina et al.
patent: 2002/0100929 (2002-08-01), Ebina et al.
patent: 2002/0127805 (2002-09-01), Ebina et al.
patent: 2003/0054610 (2003-03-01), Ebina et al.
patent: 2003/0057505 (2003-03-01), Ebina et al.
patent: 2003/0058705 (2003-03-01), Ebina et al.
patent: 2003/0060011 (2003-03-01), Ebina et al.
patent: 2003/0067032 (2003-04-01), Caprara et al.
patent: 2003/0157767 (2003-08-01), Kasuya
patent: 2003/0166320 (2003-09-01), Kasuya
patent: 2003/0166321 (2003-09-01), Kasuya
patent: 2003/0166322 (2003-09-01), Kasuya
patent: 2003/0186505 (2003-10-01), Shibata
patent: 2003/0190805 (2003-10-01), Inoue
patent: 2003/0211691 (2003-11-01), Ueda
patent: 7-161851 (1995-06-01), None
patent: B1 2978477 (1999-09-01), None
patent: 2001-156188 (2001-06-01), None
patent: 2004064012 (2004-02-01), None
U.S. patent application Ser. No. 10/636,562, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/636,581, Yamamukai, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/636,582, Inoue, filed Aug. 8, 2003.
U.S. patent application Ser. No. 10/614,985, Inoue, filed Jul. 9, 2003.
U.S. patent application Ser. No. 10/690,025, Kasuya, filed Oct. 22, 2003.
U.S. patent application Ser. No. 10/689,987, Kasuya, filed Oct. 22, 2003.
Hayashi et al. “Twin MONOS Cell with Dual Control Gates”, 2000 Symposium on VLSI Technology Digest of Technical Papers.
Chang et al. “A New SONOS Memory Using Source-Side Injection for Programming”, IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp 253-255.
Chen et al. A Novel Flash Memory Device with S Plit Gate Source Side Injection and ONO Charge Storage Stack (SPIN), 1997 Symposium on VLSI Technology Digest of Technical Papers, pp 63-64.
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3193967