Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-06-03
2004-07-20
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06766496
ABSTRACT:
BACKGROUND
Architectures for standard cell libraries, as well as gate array libraries, have become fairly standard over the years. Most common architectures employ first level power buses that run continuously through the cell. An example of such a cell is shown in
FIG. 1
, where the power rails,
101
and
102
run along the top and bottom edge of the cell. The individual cells,
100
and
103
, are placed adjacent to one another so that the power rails,
101
and
102
, run continuously from one end of the cell row to the other. In the event that there is a gap in the cell row, the bus is made to be continuous either by use of a filler cell or by routing a wire through the gap. This power bus can be called an “explicit bus” since each cell is explicitly connected to each other cell by the actual placement of the cell itself.
The cell rows themselves are tied together in a grid using other levels, as shown in FIG.
2
. The first layer busses,
110
, are strapped vertically in a second level using a wider bus,
111
. The second level is, in turn, strapped less frequently horizontally by a third layer using an even wider bus,
112
, and so on. In this structured approach, each bus of a given layer typically has the same width, regardless of the power requirements of a given section of the grid.
In
FIG. 3
, a more complete definition of the common standard cell library architecture is given. Fixed width power busses,
120
, run in first level along the top and bottom edge of the cell. These cells are referred to as “gridded cells” because they are built on a “construction grid”,
122
, which is typically defined at the via-to-via or via-to-wire spacing for the technology. This construction grid is on the order of several times the gate length of the technology used, typically from 2 to 4 times the drawn gate length. The gridded cell must have most features, including port locations,
121
, and cell boundary box,
123
, lie on the fixed construction grid. In some cases, these restrictions can make a given cell larger or more difficult to connect to than a cell built without using any type of construction grid.
In most standard cell libraries, the contents of the cells must lie entirely within the cell to avoid creating illegal interactions with adjacent cells. This is illustrated in FIG.
4
. Two cells,
130
, are placed next to one another,
138
, by placing their boundary boxes,
134
and
139
, adjacent to one another. The power busses,
131
and
137
, join together and become continuous. However, the source diffusion areas in the center,
133
and
135
, and the source contacts,
132
and
136
, cannot be shared, even though they are electrically connected to the same net.
In
FIG. 5
, examples of standard cells are shown,
140
, which contain “tap contacts”. These are electrical connections either to the well, as in
142
, or to the substrate, as in
143
. These ties electrically couple the appropriate power bus,
141
, to the respective well or substrate. While this is an electrical requirement, to include the tap contacts in the cells themselves can use valuable space and make the cell larger or limit the device sizes that can be drawn in the cells.
SUMMARY
Some embodiments include a software tool adapted to function with at least one or more cells. The one or more cells can have one or more virtual buses. The one or more cells are for an integrated circuit design. The one or more virtual buses include a plurality of ports. The plurality of ports represent a common power signal. The plurality of ports include at least two power ports on a same layer. The at least two power ports can be separated by substantially insulating material in the same layer.
Some embodiments include a software tool adapted to function with at least one or more cells. The one or more cells can have one or more virtual buses. The one or more cells are for an integrated circuit design. The one or more virtual buses include a plurality of ports. The plurality of ports share a common power signal. The plurality of ports include at least two power ports on a same layer. The at least two power ports can be separated by substantially insulating material in the same layer. The at least two power ports can be coupled together via one or more electrical paths on one or more layers of metal.
In various embodiments, the common power signal includes a fixed voltage-signal. After the at least two-power ports are coupled together by one or more electrical paths, the plurality of ports representing the common power signal can share the common power signal.
In various embodiments, an integrated circuit of the integrated circuit design is formed by one or more of a CMOS process, a Bi-CMOS process, a bipolar process, a Gallium-Arsenide process, and a Silicon-on-Insulator process.
In various embodiments, the one or more cells can include one or more of: at least one standard cell, at least one gate array cell, at least one analog cell, at least one analog mixed signal cell, at least one analog and digital cell, and at least one functional block cell.
Some embodiments include a software tool adapted to function with at least one or more virtual tap cells. The one or more virtual tap cells are for an integrated circuit design. The one or more virtual tap cells include one or more electrical couplings. The one or more electrical couplings couple to at least one of: one or more wells and one or more substrates. At least one electrical coupling of the one or more electrical couplings is positioned entirely outside one or more hierarchies of the one or more virtual tap cells.
Some embodiments can be characterized by one or more of the following: the at least one of the one or more taps is placed physically entirely in one of the one or more virtual tap cells, the at least one of the one or more taps is placed physically partly in one of the one or more virtual tap cells, the at least one of the one or more taps is placed physically partly in one of the one or more other cells, the at least one electrical coupling is positioned physically on top of the one or more virtual tap cells, and the at least one electrical coupling is positioned physically between at least two of the one or more virtual tap cells.
Some embodiments include a software tool adapted to function with at least one or more cells. The one or more cells are for an integrated circuit design. The one or more cells are adapted to have the software tool perform placement of one or more features of the integrated circuit design.
In some embodiments, the placement of at least one of the one or more features-occur primarily to place one or more electrical couplings to one or more wells and/or substrates.
In some embodiments, the placement of at least one of the one or more features occur at a granularity level of one or more electrical couplings to one or more wells and/or substrates.
In some embodiments, the software tool includes a router.
Some embodiments include a software tool adapted to function with at least one or more cells. The one or more cells are for an integrated circuit design. The one or more cells having one or more ports. The one or more ports can be adapted to couple to one or more metal substantially octagonal via structures.
In some embodiments, the one or more octagonal via structures comprises a square via cut and/or a rectangular via cut.
Some embodiments include a software tool adapted to function with at least one or more cells. The one or more cells are for an integrated circuit design. Comprised are significant features including at least one of: signal ports, power ports, and one or more boundaries of the one or more cells. The significant features are freely placed according to a minimum drawing resolution.
In some embodiments, the minimum drawing resolution corresponds to a layout grid.
In various embodiments, the significant features include signal ports, power ports, and/or one or more boundaries of the one or more cells.
Some embodiments include a software tool adapted to function with at least one or more arbitrarily shaped cel
McManus Michael J.
Rivera Billie J.
Talburt Richard
Walker William G.
Zampaglione Michael A.
Lee Granvill D
Siek Vuthe
Sierra Patent Group Ltd.
Virtual Silicon Technology, Inc.
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