Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2000-07-28
2004-09-14
Peikari, B. James (Department: 2186)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S057000, C710S029000, C711S171000, C711S172000
Reexamination Certificate
active
06792484
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to storing data in a memory with an admitting mechanism and a managing mechanism independent of each other. More specifically, the present invention is related to storing data in a memory with an admitting mechanism and a managing mechanism independent of each other.
BACKGROUND OF THE INVENTION
When using an output queuing shared memory switch architecture, it becomes necessary to maintain a detailed accounting of the shared memory that is being used to store packets in order to know exactly when to drop packets or when to permit them to enter shared memory. The decision to drop or permit packets depends on a variety of factors. In the Memory Controller ASIC, these include minimum thresholds for queues (the amount of memory an output queue is guaranteed to have for use), maximum thresholds for queues (the absolute maximum amount of memory an output queue is allowed to use), the amount of memory each queue is currently using, and the total size of the shared memory. The accounting for such a shared memory has traditionally been done in a centralized manner, where a single block of logic in an ASIC is responsible for determining whether to permit or deny a request to write to an output queue. It has also been closely tied to the shared memory itself. This approach results in moderate complexity of the logic block, as many calculations must be done to arrive at the final decision. The Independent Shared Memory Accounting of the present invention simplifies the complexity of the accounting of shared memory in the Memory Controller ASIC by breaking up the accounting into multiple parts and corresponding blocks of logic.
The Independent Shared Memory Accounting of the present invention is an improvement over existing techniques used to do accounting on an output queueing shared memory switch. The technique reduces complexity in the Memory Controller ASIC, resulting in an easier design task requiring less hardware.
SUMMARY OF THE INVENTION
The present invention pertains to an apparatus for storing data. The apparatus comprises a memory having locations where the data is stored. The apparatus comprises an admitting mechanism for admitting the data to the locations in the memory. The apparatus comprises a managing mechanism for managing and identifying which locations the data is to be stored in the memory. The managing mechanism is connected to the memory. The apparatus comprises a buffer for storing the data the admitting mechanism has admitted for storage in the memory until the managing mechanism has identified which location the data is to be stored in the memory. The buffer is connected to the admitting mechanism, the managing mechanism and the memory.
The present invention pertains to an apparatus for storing data. The apparatus comprises a memory having minimum guaranteed amounts of storage corresponding to connections. The apparatus comprises a mechanism for changing dynamically the minimum guaranteed amount. The changing mechanism is connected to the memory.
The present invention pertains to a method for storing data. The method comprises the steps of admitting data to be stored in a memory with an admitting mechanism. Then there is the step of placing the data in a buffer. Next there is the step of identifying a location in the memory the data is to be stored with a managing mechanism. Then there is the step of storing data at the location in the memory.
REFERENCES:
patent: 3806888 (1974-04-01), Brickman et al.
patent: 3820078 (1974-06-01), Curley et al.
patent: 5235692 (1993-08-01), Ayres et al.
patent: 6473435 (2002-10-01), Zhou et al.
Marconi Communications Inc.
Peikari B. James
Schwartz Ansel M.
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