Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2003-07-30
2004-09-21
Pham, Long (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S532000, C257S535000
Reexamination Certificate
active
06794702
ABSTRACT:
FIELD OF THE DISCLOSURE
The present disclosure relates to a semiconductor device and a fabrication method thereof, and more particularly, to a semiconductor device and a fabrication method thereof in which the semiconductor device includes capacitors having a metal/insulator/metal (MIM) structure.
BACKGROUND
In recent times, much research is being pursued in the area of semiconductor devices in order to realize high-capacity capacitors in analog circuits that require high-speed operation. Since conductive polysilicon is used for an upper electrode and a lower electrode in the case of a PIP structure, that is, a structure in which polysilicon, an insulator, and polysilicon are layered, an oxidation reaction occurs between contacting surfaces of a dielectric film and the upper and lower electrodes to form a natural oxidation film. The natural oxidation film reduces overall capacitance.
To remedy this problem, an MIS (metal/insulator/silicon) structure or an MIM (metal/insulator/metal) structure is used for the capacitor. The latter (i.e., the capacitor having the MIM structure) is more commonly used in semiconductor devices as a result of its low resistivity, and because such a capacitor has no internal parasitic capacitance, which is caused by depletion.
A method of fabricating a capacitor having the MIM structure according to a conventional semiconductor device manufacturing method is described herein with reference to the drawings.
FIGS. 1A
,
1
B, and
1
C, which are partial sectional views used to describe the formation of a capacitor having an MIM structure using a conventional method.
Referring first to
FIG. 1A
, a lower insulating film
2
is formed on a semiconductor substrate
1
. The lower insulating film
2
is realized using conventional semiconductor device processes and formed of an oxidation film such as PSG (phospho-silicate glass). Next, a Ti barrier layer
3
, Al lower wiring
4
, a Ti glue layer
5
, and a TiN reflection preventing film
6
are formed in this sequence on the lower insulating film
2
. Also, an SiN dielectric layer
7
, which acts as a capacitor, is formed on the TiN reflection preventing film
6
.
Subsequently, a first photosensitive film pattern is formed on the SiN dielectric layer
7
. The first photosensitive film pattern is used as a mask to selectively etch the SiN dielectric layer
7
to thereby form the SiN dielectric layer
7
to a predetermined width, after which the first photosensitive film pattern is removed and a cleaning process performed. An area of the SiN dielectric layer
7
is varied according to the desired capacitance value, and is typically approximately 10 &mgr;m by 10 &mgr;m.
Next, a second photosensitive film pattern, which has a greater width than the first photosensitive film pattern, is formed on the SiN dielectric layer
7
and the TiN reflection preventing film
6
. The second photosensitive film pattern is used as a mask such that an exposed area of the TiN reflection preventing film
6
, and predetermined areas of the Ti glue layer
5
, the Al lower wiring
4
, and the Ti barrier layer
3
under this exposed area of the TiN reflection preventing film
6
are etched. This results in the TiN reflection preventing film
6
, the Ti glue layer
5
, the Al lower wiring
4
, and the Ti barrier layer
3
being left remaining at a predetermined width. The second photosensitive pattern is then removed and a cleaning process is performed.
Subsequently, with reference to
FIG. 1B
, an HDP (high density plasma) oxidation film
8
is formed using an HDP process to fill gaps between adjacent metal wiring, after which a TEOS film
9
is formed on the HDP oxidation film
8
using conventional plasma processes. A CMP (chemical mechanical polishing) process is then performed to flatten an upper surface of the TEOS film
9
.
Next, a photosensitive film is deposited on the flattened upper surface of the TEOS film
9
, then exposure and development are performed to form a third photosensitive film pattern that exposes predetermined areas of the upper surface of the TEOS film
9
(i.e., areas where via openings will be formed). The third photosensitive film pattern is then used as a mask to perform reactive ion etching of exposed portions of the TEOS film
9
and the HDP oxidation film
8
thereunder, thereby forming via openings
100
of a predetermined width that expose an upper surface of the SiN dielectric layer
7
.
Next, with reference to
FIG. 1C
, following the removal of the third photosensitive film pattern and the performing of a cleaning process, a first barrier metal film
10
is formed along inner walls of the via opening
100
. Tungsten
11
is then formed covering the first barrier metal film
10
and completely filling the via opening
100
. Following this process, CMP is performed until the upper surface of the TEOS film
9
is exposed.
Subsequently, a Ti barrier film
12
, Al upper wiring
13
, a Ti glue layer
14
, and a TiN reflection preventing film
15
are formed in this sequence on the flattened upper surface of the TEOS film
9
and the tungsten
11
.
In the conventional method described above, aluminum is used as the wiring metal material to form the lower electrode, dielectric layer, and upper electrode of the capacitor on the lower wiring, then upper wiring is formed over these elements. The conventional capacitor therefore has a vertical structure.
However, the capacitance of the capacitor is dependent upon the contact area of the dielectric layer and the upper and lower electrodes or the thicknesses of these elements, and the areas of the upper substrate and the lower substrate must be at least as large as the contact area of the dielectric layer. Accordingly, in the case where the upper wiring, which is significantly more densely formed than the lower wiring, this condition acts to restrict the degree of integration that can be obtained.
Further, with the capacitor having such a vertical structure, because the dielectric layer is formed perpendicular to the etching direction, that is, to the direction of etching the via openings, a thickness of the dielectric layer may be altered in the process of etching. This may result in an abnormal capacitance value and ultimately cause the device to malfunction.
REFERENCES:
patent: 6249054 (2001-06-01), Tanigawa
patent: 6387775 (2002-05-01), Jang et al.
patent: 6410381 (2002-06-01), Kim et al.
patent: 6528366 (2003-03-01), Tu et al.
patent: 6559493 (2003-05-01), Lee et al.
Anam Semiconductor Inc.
Grossman & Flight LLC
Pham Long
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