Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
2001-06-22
2004-01-27
Padmanabhan, Mano (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S105000
Reexamination Certificate
active
06684311
ABSTRACT:
FIELD
The present invention is directed to memory control systems. More particularly, the present invention is directed to a memory controller that schedules commands to memory devices.
BACKGROUND
High speed data channels are known in the art for use in the transfer of data between components or circuits resident on the channel. Typically, a data channel employs a particular bus architecture with data transfer protocol defined by the architecture. The channel architecture may also have certain physical requirements to ensure that the channel operates within the required design specifications.
High speed data channels can be designed for the transfer of data between various circuitry on a single component (such as a semiconductor chip) or between two or more components. One well-known high-speed data channel architecture in use is a Rambus channel. The Rambus channel is a high-speed, byte-wide (9 bits), synchronous, chip-to-chip interconnect designed to achieve 600 Mega bytes per second (MB/sec) and greater data transfer rates between components on the channel. One specific Rambus channel, referred to as the Direct Rambus channel, is specified to transfer data at 1.6 Giga bytes per second (GB/sec) between components on the channel. In order to operate on the channel, the various components on the Rambus channel must interface with the channel and meet the stringent requirements imposed on these components, which are referred to as Rambus components.
The Rambus system may specify parameters in terms of two different clocks, namely a RCLK clock and a SCLK clock. The common clock (SCLK) may run between 75 MHz and 100 MHz, while the faster clock (RCLK) runs at four times this speed (from 300 MHz to 400 MHz).
Rambus dynamic random access memory (RDRAM) devices may have certain restrictions that disallow presentation of commands without minimum intervals between the commands. For example, page maintenance operations such as Open and Close may not be presented to the same RDRAM device within two SCLK signals (or eight RCLK clock signals) of one another.
Restrictions between page maintenance operations and memory operations may have less convenient transmission restrictions. An example of inconvenient scheduling is scheduling bus turnarounds when accesses are presented to more than one RDRAM device. These turnarounds typically require only a single RCLK cycle; however, a SCLK-granular scheduling algorithm can cause the system to lose four entire RCLKs worth of bandwidth every time the RDRAM controller needs to obtain data from two different RDRAM devices.
REFERENCES:
patent: 6169436 (2001-01-01), Marbot
patent: 6317806 (2001-11-01), Audityan et al.
patent: 6374323 (2002-04-01), Stracovsky et al.
Inoa Midys
Intel Corporation
Kenyon & Kenyon
Padmanabhan Mano
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