Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2001-06-19
2004-09-28
Lamarre, Guy J. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S006130, C714S785000, C711S111000, C370S338000, C370S352000
Reexamination Certificate
active
06799293
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to computer memory access arbitration. In particular the present invention relates to the efficient handling of write requests in connection with error correction code.
BACKGROUND OF THE INVENTION
In computer systems utilizing high speed synchronous dynamic random access memory (SDRAM), there is at least some latency between the time a new memory access is requested and the time that data can actually start flowing to or from the memory. This latency is due to the way that SDRAM operates. In particular, before a read or write operation can begin, a bank (row) in the memory must first be activated. Next, a read or write command can be issued along with the remainder of the address that is being accessed. Data transfers can begin only after these steps have been taken.
An additional period latency is involved if an error correction code (ECC) is used. This is because write data must pass through the ECC logic in order to create a syndrome value based on the data that is being written. The data and syndrome value are then written together. The additional processing required by an error correction code typically adds from 10 to 15 clocks of latency during a read-modify-write operation from the start of an access request to the first cycle in which a data transfer occurs.
In many devices that access SDRAM, there are multiple internal clients that may require access to the SDRAM. Often, an arbitration module is provided to determine which of the clients has access to the memory at any given point in time. However, because of the latency described above, there is typically a gap between the end of one client's access to the memory and the beginning of another access to the memory. During this period of latency, the memory interface is unused. This latency reduces the overall performance of the computer system.
Memory controllers that include arbiters to determine which of the clients will be granted access to the memory next, and that track whether that client will be writing to or reading from the memory, have been developed. Such systems, which are often capable of determining the next client to be granted access while a previous access is still in progress, can improve the performance of the computer system. In general, the performance improvement comes from allowing the memory controller to begin the steps required to prepare for the next client access internally while the previous access is still in progress.
The performance of the memory controller may be additionally refined by having the clients provide transaction size information to the arbiter, so that the arbiter can determine when that client's transaction is nearing completion. The arbiter can then determine which client will be granted access next, and can forward the address and read or write information to the memory controller for the next transaction, while a current transaction is still in progress.
In order to improve the reliability of systems that store information in SDRAM, error correction code is often used. In a typical ECC scheme, an 8 bit syndrome value is appended to each 64 bit word of data that is written to the SDRAM. The syndrome value is created based on the 64 bit data word value. When the data and syndrome value are read back from memory, the memory controller calculates a new syndrome value from the data that was read. The new syndrome value is compared to the syndrome value that was also read from the SDRAM. If the syndrome values match, the data is presumed to be correct, and it is passed to the appropriate client. If there is a difference between the syndrome values, an error in the data is indicated. Depending on the algorithm employed and the type of data error, the error may be correctable based on the information provided by the syndrome value.
One drawback of using this type of error correction code occurs in connection with a sparse byte enable condition. A sparse byte enable condition occurs when less than a complete 64 bit word is to be written to memory. A less than complete data word may be received when the address specifying a first word in a block of data to be written is unaligned. A sparse byte enable condition is typically signaled by byte enable bits that are provided with the data. In particular, the byte enable bits signal which of the 8 bytes in the 64 bit block of data are to be written. When a sparse byte enable condition is encountered, the data word cannot be written directly to memory. Instead, a read-modify-write sequence must be used. This sequence is necessary to allow the memory controller to create a new ECC syndrome value to be written to memory along with the data. The new ECC syndrome value is calculated from a combination of the original data read from the memory and the bytes of new data that are to be written. That is, the older data is used as filler to form a complete 64 bit data word. As can be appreciated, the complete data word must be formed before the otherwise incomplete data is stored, in order to calculate a valid ECC syndrome value.
Conventional memory controllers are not informed that a block of data is in a sparse byte enable condition until that block of data is received. Therefore, when the memory controller is expecting to write data, and has prepared for a write operation, additional clocks of latency are incurred if sparse byte enables are received, as the memory controller must terminate the steps begun for a write operation, and instead read old data from the memory.
Therefore, it would be desirable to provide a method and an apparatus for controlling access to memory that remove or reduce the additional period of latency incurred when a write operation involving less than a complete data word is encountered. Furthermore, it would be advantageous to provide a method and an apparatus for controlling access to memory that were inexpensive to implement and reliable in operation.
SUMMARY OF THE INVENTION
In accordance with the present invention, a high speed memory access arbitration method and apparatus that include a sparse byte enable indication are provided. The present invention generally allows a memory interface included as part of a memory controller or RAID controller to appropriately prepare for a write to memory when the first block of data to be written includes less than a complete data word. In particular, the present invention provides a memory interface that, upon receipt of an indication that a first block of data to be written contains less than a complete data word, initiates a read from memory. Therefore, old data read from memory can be available at about the same time the first block of data to be written is received. The old data can be combined with first block of data to be written to form a complete data word, and an ECC syndrome value can be calculated. The complete data word and ECC syndrome value can then be written to memory.
According to an embodiment of the present invention, a sparse byte enable condition is signaled to the memory interface of the controller by a client or device when the client or device issues a write request that involves a first block of data having less than a complete data word. In response to receiving the sparse byte indication, the memory interface initiates a read of old data from the memory. The old data read from memory is combined with the data to be written to form a complete data word. The complete data word includes all of the data to be written as part of the first block of data, and portions of the block of old data read from memory. An error correction syndrome value is calculated from the complete data word, and the complete data word and syndrome value are written to memory.
According to another embodiment of the present invention, a write request is produced in an external device that includes an indication that a first block of data identified in connection with the write request contains less than a complete data word. The write request is provided to a first data interface included in the controller. In re
Klobcar James R.
Peters Michael J.
Adaptec, Inc.
Lamarre Guy J.
Sheridan & Ross P.C.
LandOfFree
Sparse byte enable indicator for high speed memory access... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Sparse byte enable indicator for high speed memory access..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Sparse byte enable indicator for high speed memory access... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3188042