Dynamic modulation of on-chip supply voltage for low-power...

Details Dynamic modulation of on-chip supply voltage for low-power... Dynamic modulation of on-chip supply voltage for low-power...

2002-05-28

2004-05-18

Williams, Howard I (Department: 2819)

Electricity: power supply or regulation systems

Output level responsive

Using a three or more terminal semiconductive device as the...

C341S155000

Reexamination Certificate

active

06737844

ABSTRACT:

BACKGROUND OF INVENTION
Modern high performance microprocessors have an ever-increasing number of circuit elements and an ever-rising clock frequency. Also, as the number of circuits that can be used in a central processing unit (CPU) has increased, the number of parallel operations has risen. As CPU performance continues to increase, the result has been a larger number of circuits switching at faster rates.
Higher frequencies and data throughput cause a processor to consume increased power. The power dissipated by a circuit is a quadratic function of the supply voltage. Reducing the supply voltage may decrease the power dissipated by a circuit; however, reducing the supply voltage also increases the delay of the circuit. Slowing the speed of the circuit may cause some CPU activities to be incomplete at the end of a cycle. The effect may lead to loss of data in a CPU or incorrect results. Thus, from a design perspective, power is an important consideration. Power is a consideration in the design of a broad range of integrated circuits, including CPUs.
In
FIG. 1
, an integrated circuit (
100
) is shown with connections to an external supply voltage terminal (
101
) and external ground voltage terminal (
103
). The external supply voltage terminal (
101
) and external ground voltage terminal (
103
) are used to provide power to the integrated circuit (
100
). A circuit (
120
) located on the integrated circuit (
100
) performs some function necessary for the operation of the integrated circuit (
100
).
A supply voltage routing line (
105
) and a ground voltage routing line (
107
) are used to provide power to the circuit (
120
) by connecting to the external supply voltage terminal (
101
) and external ground voltage terminal (
103
), respectively. Routing lines have a resistance and form capacitances with adjacent routing lines. These parasitics created by the supply voltage routing line (
105
) are modeled by impedance Z
A
(
122
). The parasitics created by the ground voltage routing line (
107
) are modeled by impedance Z
B
(
124
).
Due to switching noise created by the active switching of circuits, e.g., circuit (
120
) on the integrated circuit (
100
), decoupling capacitors are added to act as local power supplies. For example, a decoupling capacitor (
102
) is located physically close to the external supply voltage terminal (
101
) and external ground voltage terminal (
103
) to reduce the amount of power supply noise. Power supply noise from the external supply voltage terminal (
101
) and external ground voltage terminal (
103
) may be generated by other integrated circuits connected to the external supply voltage terminal (
101
) and external ground voltage terminal (
103
).
In
FIG. 1
, decoupling capacitor (
108
) is located physically close to the circuit (
120
) to reduce the amount of power supply noise on the supply voltage routing line (
105
) and ground voltage routing line (
107
). The power supply noise on the supply voltage routing line (
105
) and ground voltage routing line (
107
) may be generated by active circuits, e.g., circuit (
120
), located on the integrated circuit (
100
).
The power dissipated by a circuit, for example circuit (
120
), is a quadratic function of a voltage difference, e.g., the voltage difference between the voltage on the supply voltage routing line (
105
) and the voltage on the ground voltage routing line (
107
). In particular, power is equal to the capacitance of the load multiplied by the frequency of switching multiplied by the square of the voltage difference. That is, P=C
L
fV
DD
2
, where P is power, C
L
is the capacitance of the load, and V
DD
is the voltage difference. Reducing the voltage difference may reduce the power dissipated; however, reducing the voltage difference also increases the delay of a circuit, such as the circuit (
120
) in FIG.
1
.
SUMMARY OF INVENTION
According to one aspect of the present invention, an integrated circuit comprises a first power supply grid; a modulation circuit arranged to receive a first voltage from the first power supply grid where the first voltage is modulated by the modulation circuit to produce a second voltage not greater than the first voltage on a second power supply grid; and a digital register operatively connected to the modulation circuit where the digital register determines a desired second voltage of a circuit connected to the second power supply grid and controls the modulation of the modulation circuit.
According to one aspect of the present invention, a method of supplying power to an integrated circuit comprises modulating a first voltage from a first power supply grid to produce a second voltage not greater than the first voltage on a second power supply grid; determining a desired second voltage on the second power supply grid based on an activity level of a circuit connected to the second power supply grid; maintaining a digital value representative of the desired second voltage on the second power supply grid; and adjusting the desired second voltage based on the digital value.
According to one aspect of the present invention, an integrated circuit, comprises means for modulating a first voltage from a first power supply grid to produce a second voltage not greater than the first voltage on a second power supply grid; means for determining a desired second voltage on the second power supply grid based on an activity level of a circuit connected to the second power supply grid; means for maintaining a digital value representative of the activity level of the circuit connected to the second power supply grid; and means for adjusting the desired second voltage based on the digital value.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.


REFERENCES:
patent: 3153142 (1964-10-01), Hellerman
patent: 5774734 (1998-06-01), Kikinis et al.
patent: 6292902 (2001-09-01), Drobnik
patent: 6639391 (2003-10-01), Huang et al.
patent: 2002/0000928 (2002-01-01), Heyl et al.
patent: 2002/0118001 (2002-08-01), Duffy et al.
patent: 10035418 (2002-02-01), None

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