Semiconductor device

Details Semiconductor device Semiconductor device

2003-04-08

2004-01-13

Prenty, Mark V. (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S368000

Reexamination Certificate

active

06677633

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device. More specifically, the present invention relates to a semiconductor device including a highly integrated memory using memory cells having an amplification function.
BACKGROUND ART
A dynamic random access memory (DRAM) is widely used as a highly integrated, high-speed memory for a main memory of a personal computer. One-transistor one-capacitor (1T1C) cell having one transistor and one capacitor is used as a memory cell. In recent semiconductor devices, an operating voltage is reduced due to low pressure resistance with finer MOS transistors and low power consumption. Along with it, in a DRAM using one transistor cell, since a memory cell itself has no amplification function, the read signal amount from the memory cell is small and the operation subject to various noises is easily unstable.
As a memory cell which can obtain a large read signal amount by an amplification function, attention is focusing again on the so-called gain cell having an amplification function which has been used before practical utilization of one-transistor cell.
Gain cells are described in IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 10-11, 1972 (hereinafter referred to as reference 1) and IEEE International Solid-State Circuits Conference, DIGEST OF TECHNICAL PAPERS, pp. 12-13, 1972 (hereinafter referred to as reference 2). These are memory cells each having three transistors (hereinafter referred to as a 3-transistor cell) arranged on a silicon surface.
As a gain cell of a new structure, a memory cell having two transistors and one capacitor is proposed in IEE ELECTRONICS LETTERS 13th May 1999 Vol.35 No.10) (hereinafter referred to as reference 3). The memory cell shown in FIG. 4 of the reference 3 may realize very excellent data hold properties by low leak transistors of a vertical type structure. In addition, since the memory cell is of a structure integrating two transistors and one capacitor with each other, it is integrated more highly than the 3-transistor cells of the references 1 and 2.
The memory cell of the reference 3 has a MOS transistor body and four terminals of a wordline, a bitline, a sensing line and a ground voltage. These must be connected to wires, requiring contacts for connection. In consideration of mask alignment accuracy, the cell area may be large. Means for preventing this is not described in the reference 3.
The reason why a DRAM is used widely is that its highly integrated 1T1C cells make the chip area small and its bit unit cost is lower than that of a static random access memory. In order that a memory using the memory cells as shown in the reference 3 may be accepted widely in the market, high integration equal to or more than that of the DRAM is desired.
An object of the present invention is to provide a semiconductor device having a small-area memory which can realize highly integrated memory cells having an amplification function and be operated fast at a low voltage.
DISCLOSURE OF THE INVENTION
Representative inventions disclosed by this application will be described as follows.
To achieve the above object, a semiconductor device according to the present invention has:
a data line (data line DL in
FIG. 1
of the later-described embodiment);
a first wordline (WL
0
) crossing the data line;
a second wordline (WL
1
) crossing the data line;
a first memory cell (MC
0
) provided at the crossing point of the data line and the first wordline; and
a second memory cell (MC
1
) provided at the crossing point of the data line and the second wordline,
wherein
the first memory cell has:
a first transistor (M
0
) being a signal path at writing;
a second transistor (M
1
) being a signal path at reading; and
a first storage node (N) holding information by storing electric charge,
the second memory cell has:
a third transistor (M
0
) being a signal path at writing;
a fourth transistor (M
1
) being a signal path at reading; and
a second storage node (N) holding information by storing electric charge,
the read signal path from the fourth transistor to the data line includes the second transistor.
In this case, preferably, the gate of the first transistor is connected to the first wordline, and the gate of the third transistor is connected to the second wordline. Further, preferably, one source/drain terminal of the first transistor is connected to the data line and the other is connected to the first storage node, one source/drain terminal of the third transistor is connected to the data line, and the other is connected to the second storage node.
In addition, a semiconductor device according to the present invention has:
a write data line (data line DLW in
FIG. 37
of the later-described embodiment);
a read data line (DLR);
a first wordline (WL
0
) crossing the write data line and the read data line;
a second wordline (WL
1
) crossing the write data line and the read data line;
a first memory cell (MC
0
) provided at the crossing point of the write data line and the first wordline; and
a second memory cell (MC
1
) provided at the crossing point of the write data line and the second wordline,
wherein
the first memory cell has:
a first transistor (M
0
) being a signal path at writing;
a second transistor (M
1
) being a signal path at reading; and
a first storage node (N) holding information by storing electric charge,
the second memory cell has:
a third transistor (M
0
) being a signal path at writing;
a fourth-transistor (M
1
) being a signal path at reading; and
a second storage node (N) holding information by storing electric charge,
the read signal path from the fourth transistor to the read data line includes the second transistor.
In this case, preferably, the write data line and the read data line are configured by different wiring layers.


REFERENCES:
patent: 5606189 (1997-02-01), Adan
patent: 5675160 (1997-10-01), Oikawa
patent: 6570206 (2003-05-01), Sakata et al.
patent: 3543937 (1985-12-01), None
patent: 0 224 213 (1986-11-01), None
patent: 03224265 (1990-01-01), None
patent: 04003463 (1990-04-01), None
patent: 04147490 (1990-10-01), None
patent: 08250673 (1995-03-01), None
patent: 2000-113683 (1998-10-01), None
J. A. Karp, W. M. Regitz, and S. Chou, “Memory I: A 4096-Bit Dynamic MOS RAM,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1972, pp. 10-11.
W. Martino and B. F. Croxon, “Memory I: The Inverting Cell Concept for MOS Dynamic RAMS,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, 1972, pp. 12-13, and 208.
K. Nakazato, K. Itoh, H. Mizuta and H. Ahmed, “Silicon Stacked Tunnel Transistor For High-Speed and High-Density Random Access Memory Gain Cells,” Electronic Letters, May 13, 1999, vol. 35, No. 10.
Shoji Shukuri, Tokuo Kure, Takashi Kobayashi, Yasushi Gotoh, and Takashi Nishida, “A Semi-Static Complementary Gain Cell Technology For Sub-1 V Supply DRAM's,” IEEE Transactions on Electron Devices, Jun. 1994, vol. 41, No. 6, pp. 926-931.
International Search Report in Japanese of Jul. 4, 2000.

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