Complementary pass transistor based flip-flop

Details Complementary pass transistor based flip-flop Complementary pass transistor based flip-flop

2003-03-25

2003-11-11

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S211000, C327S212000, C327S218000

Reexamination Certificate

active

06646492

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to flip-flops, and more particularly, to a complementary pass transistor based flip-flop (CP flip-flop) which is smaller than a conventional low-power flip-flop, and is operable at a high speed in an active mode with reduced power consumption and can latch data in a sleep mode with minimum power consumption.
2. Description of the Related Art
FIG. 1A
is a circuit diagram of a conventional transmission gate master-slave flip-flop (TGFF). Referring to
FIG. 1A
, the FGFF consists of a master stage on the left of a dashed line and a slave stage on the right of the dashed line. When a clock signal Clk is high, the master stage receives and latches input data, and the slave stage latches and outputs the previous logic state. When the clock signal Clk is low, the master stage no longer receives the input data, and the slave stage receives and outputs the logic state passed from the master stage. In
FIG. 1A
, Vdd denotes a high supply voltage, GND denotes ground voltage, Clkb denotes an inverted clock signal, and Q denotes a positive output node.
FIG. 1B
is a circuit diagram of a conventional hybrid latch flip-flop (HLFF). Referring to
FIG. 1B
, the HLFF consists of a dynamic front stage on the left of a dashed line and a static back stage on the right of the dashed line.
When a clock signal Clk goes from a high level to a low level, an inverted clock signal Clkb is delayed by three inverters. During the delay period, input data Data is passed to the front stage, and the front stage is charged or discharged, or remains at the previous logic state. The back stage remains at the previous logic state.
When the clock signal Clk goes from a low level to a high level, the front stage no longer receives the input data Data, and the back stage outputs the previous logic state.
FIG. 1C
is a circuit diagram of a conventional semi-dynamic flip-flip (SDFF). Referring to
FIG. 1C
, the SDFF consists of a precharge stage on the left of a dashed line, and an output buffer stage on the right of the dashed line. When an input data Data is high, the precharge stage is fully discharged so that an output Q_b becomes high. When the input data Data is low, the precharge stage is charged to a logic high state, and the output Q_b becomes low.
FIG. 1D
is a circuit diagram of a conventional sense amplifier flip-flop (SAFF). Referring to
FIG. 1D
, for the SAFF, when a clock is high, a voltage level of the input signal Data is stored in a latch circuit including two NAND gates and then is output. When the clock is low, outputs Q and Qb remain at the previous state regardless of the state of the input signal Data received.
In the conventional flip-flops described above, the master stage or the dynamic front stage needs to be precharged so that power consumption is considerable. Currently available systems need high-speed and low power consumption. However, use of the conventional flip-flops increases layout area and power consumption.
When a multi-threshold complementary metal oxide silicon (MTCMOS) technique is applied to the conventional flip-flops, the conventional flip-flops are available in the active and sleep modes of a system which includes a power-down circuit that suspends operation by cutting off the supply power. In this case, there is a need for a circuit for retaining latched data when the supply power is cut off. In addition, there is a drawback in that designing control signals for data storage is more complicate.
According to the MTCMOS technique, a MOS switch having a relatively high threshold voltage is serially connected between the power supply voltage Vdd, Vss, or GND and a logic circuit. Depending on whether the MOS switch is opened or closed, the power supply voltage is supplied to the logic circuit, which is formed by an NMOS transistor having a relatively low threshold voltage, or is cut off, thereby reducing power consumption. In particular, in the active mode, the MOS switch is turned on to supply the power supply voltage to the logic circuit. In the sleep mode, the MOS switch is turned off to stop the supply power being provided to the logic circuit, thereby minimizing power consumption of the overall system.
The MTCMOS technique is highly effective to reduce power consumption by circuits in a system in which the sleep mode is relatively longer than the active mode. However, if a special measure for the power cut-off period is not considered, data stored in a latch circuit or a flip-flop would be lost.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is a first object of the present invention to provide a complementary pass transistor based flip-flop (CP flip-flop) which has a smaller layout area than a conventional low-power flip-flop and is operable at a high speed with reduced power consumption.
It is a second object of the present invention to provide a CP flip-flop in which data can be latched in the sleep mode without need for an additional circuit for retaining latched data, and power consumption is also minimized.
To achieve the first object of the present invention, there is provided a complementary pass transistor based flip-flop comprising: a clock delay unit for inverting and delaying a clock signal; a switch unit for switching input data in response to the clock signal and an output signal of the clock delay unit; and a latch unit for latching at least one output signal of the switch unit.
In a first embodiment of the CP flip-flop, the clock delay unit may include an odd number of inverters connected in series for inverting the clock signal. The switch unit may include a first switch for switching the input data in response to the clock signal, and a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit. The latch unit may include a first inverter having an input port connected to the second switch of the switch unit, and a second inverter having an input port connected to an output port of the first inverter and an output port connected to the input port of the first inverter.
In a second embodiment of the CP flip-flop, the CP flip-flop may further comprise a first inverter for inverting the input data. The clock delay unit may include an odd number of inverters connected in series for inverting and delaying the clock signal. The switch unit may comprise: a first switch for switching the input data in response to the clock signal; a second switch for switching an output signal of the first switch in response to the output signal of the clock delay unit; a third switch for switching an output signal of the first inverter in response to the clock signal; and a fourth switch for switching an output signal of the third switch in response to the output signal of the clock delay unit. The latch unit may comprise a second inverter having an input port connected to the second switch of the switch unit and an output port connected to the fourth switch; and a third inverter having an input port connected to the fourth switch of the switch unit and an output port connected to the second switch.
In a third embodiment of the CP flip-flop, the clock delay unit inverts and delays the clock signal in response to an enable signal. The switching unit may include a first switch for switching the input data in response to the clock signal and a second switch for switching an output signal of the first switch. The latch unit may include a logic circuit and a latch circuit. The logic circuit may include a NAND gate that responds to a set signal and a reset signal. The latch circuit may include first and second inverters for latching the input data and four NMOS transistors that respond to a set signal and a reset signal.
In a fourth embodiment of the CP flip-flop, the CP flip-flop may further include a first inverter for inverting the input data. The clock delay unit may invert and delay the clock signal in response to an enable signal. The switch unit may include: a first switch for switching the input data in respon

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