Optics: measuring and testing – By alignment in lateral direction – With registration indicia
Reexamination Certificate
1999-10-21
2003-12-30
Font, Frank G. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
With registration indicia
Reexamination Certificate
active
06671048
ABSTRACT:
TECHNICAL FIELD
The present claimed invention relates to the field of semiconductor wafer fabrication. Specifically, the present claimed invention relates to a method for determining wafer misalignment using a pattern on a fine alignment target.
BACKGROUND ART
Integrated circuits (ICs) are fabricated en masse on silicon wafers using well-known photolithography, etching, deposition, and polishing techniques. These techniques are used to define the size and shape of components and interconnects within a given layer built on a wafer. The IC is essentially built-up using a multitude of interconnecting layers, one formed on top of another.
Accurate formation of an image on a wafer using photolithography involves several categories. One of the most important categories is alignment. Precise alignment between the succeeding layers formed on the wafer is critical. For example, precise alignment is necessary to accurately couple interconnects, to ensure proper location of insulators, and to accurately shape and size devices to achieve proper performance. Hence, a need arises for ensuring accurate alignment of multiple layers formed on a wafer.
Referring now to Prior Art
FIG. 1A
, a reticle
100
a
having multiple patterns is presented. Reticle
100
a
uses a conventional alignment pattern. Specifically, the alignment pattern includes a fine alignment target
108
a,
an overlay box
102
a,
and a product wafer pattern
106
. Product wafer patterns form the devices and interconnections in a layer of material on the wafer, while the conventional alignment patterns
108
a
and
102
a
provide patterns in the layer of material on the wafer by which subsequent layers of material on the wafer may be accurately aligned.
The conventional alignment pattern shown in prior art
FIG. 1A
uses two separate kinds of features to accomplish alignment and measurement of misalignment. The first feature is an alignment target
108
a,
that typically includes a plurality of rectangles
109
a.
The second feature is an overlay box
102
a.
In the present case, only a large overlay box
102
is shown. Alignment target
108
a
is used to coarsely align a wafer in a stepper machine for a subsequent fabrication operation. Subsequent to the initial placement of the wafer, images or structures are created on the wafer using two separate overlay box patterns. Box
102
a
is the large version of the two boxes used for the misalignment measurement.
Referring now to prior art
FIG. 1B
, a reticle with an alignment pattern that complements the pattern of prior art
FIG. 1A
is shown. The alignment pattern of prior art
FIG. 1B
is used to create structures on the wafer following the application of the prior art
FIG. 1A
pattern on the wafer. Alignment pattern of prior art
FIG. 1B
includes small overlay box
104
b,
fine alignment target
108
b,
and large overlay box
102
b.
Referring now to prior art
FIG. 1C
, a wafer having a conventional alignment target and a conventional large overlay box is shown. Conventional alignment target
118
a
and large overlay box
112
a
is typically formed in a scribe line
110
of a product wafer so as not to interfere with the product patterns, e.g. ICs, formed on the dies. Reticle
100
a
of prior art
FIG. 1A
is used to form alignment target
118
a
and large overlay box
112
a
in wafer
100
c.
Referring now to prior art
FIG. 1D
, a wafer having conventional alignment targets and conventional small and large overlay boxes formed therein is shown. Wafer
100
c
of
FIG. 1D
is the same wafer
100
c
of
FIG. 1C
, but with new structures formed thereon, typically on a next layer of material deposited on the wafer. Reticle
100
b
of prior art
FIG. 1B
is used to form new structure such as small overlay box
114
b,
fine alignment target
118
b,
and large overlay box
112
b.
By examining the alignment between large overlay box
112
a
and small overlay box
114
b,
an alignment error, e.g. unequal gap between the boxes, and subsequent correction can be determined. For each subsequent product pattern formed on a new layer of material, a reticle such as the one in prior art
FIG. 1B
, can be used to form the new pattern of a small overlay box, a fine alignment target, and a large overlay box. However, by requiring all these structures for each layer, a great deal of space in the scribe line
110
is consumed. This space within the scribe line
110
is highly sought after for implementing structures and processes that monitor fabrication operations on the wafer, besides alignment. For example, functional structure is often created within the scribe lines to evaluate the electrical performance of each layer during the fabrication operation. As a result of these limitations, a need exists to reduce the size and quantity of the alignment structures, and the space which they consume, on the wafer.
Additionally, the conventional method of using separate components for aligning and measuring misalignment confounds the misalignment measurement. Specifically, the conventional method, as shown in prior art FIG.
1
A through
FIG. 1D
, uses an alignment target structure for aligning the wafer in the stepper, and uses a separate set of overlay boxes for measuring the misalignment. Because of the offset
120
between the two structures, confounding errors can arise. For example, lens aberration or rotational error will be different for different areas of the reticle projected onto different areas of the wafer. Consequently, the misalignment measurement between large overlay box
112
a
and small overlay box
114
b
on wafer
100
c
might include an error caused by lens aberration. That is, a lens aberration existing in the area corresponding to the overlay boxes, that does not exist for the fine alignment target, will confound the results of the alignment process. That is, if the same lens aberration did not exist at the location of the fine alignment target, then additional error is included in the misalignment measurement. If a misalignment correction is made to align the boxes, based on the confounded misalignment measurement, then the balance of the patterns formed by the reticle may be incorrectly aligned. Consequently, a need arises for a method and apparatus that more accurately determines misalignment.
In the prior art, alignment between two different patterns on two different layers was not directly tied together. Instead, each layer was aligned to the previous layer. Hence, the misalignment error would accumulate over the quantity of layers that separated the two layers that required close alignment to each other. The accumulation of misalignment can result in an unacceptable error for a given device formed on a wafer. Hence, a need arises for a method and apparatus providing very accurate alignment between two patterns on two different layers on a wafer, regardless of the quantity of layers between them.
In summary, a need arises for ensuring accurate alignment of multiple layers formed on a wafer. Additionally, a need exists to reduce the size and quantity of the alignment structures, and the space which they consume, on the wafer. And, a need arises for a method and apparatus that more accurately determines misalignment. Furthermore, a need arises for a method and apparatus providing very accurate alignment between two patterns on two different layers on a wafer, regardless of the quantity of layers between them.
DISCLOSURE OF THE INVENTION
The present invention provides a method and apparatus for ensuring that the different layers of an IC that are formed on a wafer are accurately formed. Furthermore, the present invention ensures accurate alignment of multiple layers formed on a wafer. Additionally, the present invention provides a method that directly checks for misalignment between the layer formed by an overlay in a stepper to the alignment targets on the wafer. The present invention also reduces the size and quantity of the alignment structures, and the space which they consume, on the wafer. And the present invention provides a method and apparatus providing very a
Font Frank G.
Koninklijke Philips Electronics , N.V.
Lee Andrew H.
Zawilski Peter
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