Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2002-06-24
2003-11-18
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06651127
ABSTRACT:
BACKGROUND
The invention relates generally to computer system data transfer operations and, more particularly, to the detection of a data transfer termination action.
Graphics capable computer systems may be characterized by their ability to rapidly generate and manipulate graphical images. In general, graphical rendering performance improves with increased memory availability (i.e., quantity) and bandwidth (i.e., access speed). As three dimensional rendering hardware and software become more pervasive, the need for larger faster memories will likely accelerate. One approach to meeting the memory requirements of graphical processing computer systems is through the use of a special purpose memory interface. For example, the Accelerated Graphics Port (AGP) specification from Intel Corporation defines a component level interface to facilitate the use of computer system memory during graphical processing operations. (See the “Accelerated Graphics Port Interface Specification,” Revision 2.0, 1998).
One feature of the AGP interface is that it provides three data transfer rates: 1×, 2×, and 4×. In the 1× transfer mode, a master device may transfer data transfer requests to a target device at a clocking frequency of 66 MHz—corresponding to the operational speed of a standard 66 MHz PCI-type bus. (See the “PCI Local Bus Specification,” Revision 2.2, 1999; available from the PCI Special Interest Group). In the 2× transfer mode, master to target data requests are transferred at a clocking frequency of 133 MHz, and in the 4× transfer mode, data requests transfer operations occur at a clocking frequency of 266 MHz. 2× and 4× transfer modes are realized through the use of “sideband” signals. For example, the sideband address (SBA) bus and associated sideband strobe signals may be used to enqueue AGP commands from an AGP master to an AGP target. In a typical implementation, an AGP master is a plug-in card and an AGP target is integrated within the processor-to-PCI bus bridge circuit.
Referring to
FIG. 1
, in accordance with the current AGP specification, AGP master
100
may transfer data requests to AGP target
102
via SBA bus
104
under control of master driven strobe signals
106
. In addition, the AGP specification defines AGP clock signal
108
as the fundamental control clock for an AGP interface. AGP clock
108
is used to transfer data requests on SBA bus
104
in the 1× mode. When in either the 2× or 4× transfer modes, SBA bus
104
operates at two different data rates in a time multiplexed fashion: 66 MHz and 133 MHz in the 2× mode; 66 MHz and 266 MHz in the 4× mode. The low-speed (66 MHz) rate is used by AGP master
100
to initiate a synchronization event by driving SBA bus
104
with a 0× FE value. Two AGP clock cycles later, master
100
begins strobing data (via strobe signal
106
) into AGP target
102
at one of the high-speed rates, 133 MHz or 266 MHz. Thereafter, AGP master
100
may continuously transfer data (i.e., data requests) to AGP target
102
. Prior to terminating its transfer operation, AGP master
100
is required to drive SBA bus
104
with a NOP pattern for a minimum of four AGP clock cycles. (While a master is required to transmit at least four NOPs prior to terminating a transfer operation, such an action does not guarantee termination—master
100
may resume transferring data even after it transmits the required NOPs). If AGP master
100
does terminate its data transfer operation, it is required to drive strobe signal
106
to a specified state (high, for example) for a minimum of eight AGP clock cycles. Only then may master
100
initiate another synchronization event.
At least two factors complicate the ability of AGP target
102
to determine when a SBA bus data transfer operation has been terminated by master
100
. First, AGP master
100
may resume transferring data even after transmitting four or more NOPs. Thus, target
102
may not use the presence of the required NOPs to detect the end of a data transfer operation. Second, the state of SBA port signals (e.g., SBA bus
104
and strobe signal
106
) are undefined relative to AGP clock
108
during SBA bus data transfer operations. Thus, the AGP clock may not be used by target
102
to directly sample the state of strobe signal
106
to detect the end of a data transfer operation. Without the ability to reliably detect when a SBA bus data transfer operation has stopped, target device
102
may not detect subsequent synchronization events. Missed synchronization events may, in turn, cause a general malfunction of the AGP interface.
Thus, it would be beneficial to provide a technique to detect when an AGP master device has terminated a SBA bus data transfer operation.
SUMMARY
In one embodiment, the invention provides a circuit to detect when an accelerated graphics port master device terminates a sideband bus data transfer operation. The circuit includes a first register to cyclically generate a predetermined sequence of output signals at a rate determined by a first clock signal, a second register to cyclically generate the predetermined sequence of output signals at a rate determined by a second clock signal (each output signal of the second register having a corresponding first register output signal), and a detector to detect a mismatch between an output signal from the second register and a corresponding output signal from the first register. In other embodiments, the invention provides a bridge circuit and a computer system incorporating a circuit as described above.
REFERENCES:
patent: 5905509 (1999-05-01), Jones et al.
patent: 6047334 (2000-04-01), Langendorf et al.
patent: 6418502 (2002-07-01), Larson
patent: 57-83836 (1982-05-01), None
patent: 1-236341 (1989-09-01), None
Auve Glenn A.
Trop Pruner & Hu P.C.
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