Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
2002-03-25
2003-11-25
Le, Don (Department: 2819)
Electronic digital logic circuitry
Interface
Current driving
C326S090000, C326S026000
Reexamination Certificate
active
06653863
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to electrical buses.
BACKGROUND OF THE INVENTION
The I2C bus was developed in the early 1980's to provide an easy way to connect a computer processor unit (CPU) to other peripheral semiconductor devices located in a television set.
Normal computer systems typically use byte-wide or wider buses to accomplish this task. This solution results in a large number of copper tracks on printed circuit boards (PCBs) to route the address and data lines required, not to mention a number of address decoders and logic required to connect everything. In mass production items such as television sets, video cassette recorders (VCRs), and audio equipment, this is not an acceptable solution. In these products, every component counts—and one component fewer means more money for the manufacturer and less expensive products for the customer.
Furthermore, a large number of control lines imply that a system is more susceptible to disturbances by Electromagnetic Compatibility (EMC) and Electrostatic Discharge (ESD). The research done by Philips Labs in Eindhoven (The Netherlands) resulted in a two-wire communication bus called the I2C bus. I2C is an acronym for Inter-IC bus. The I2C bus' name literally explains its purpose: to provide a communication link between integrated circuits.
Today, the extent of this I2C bus goes much further than audio and video equipment. The I2C bus is generally accepted in the electronics industry. Offspring of the I2C bus, such as D2B bus and ACCESS bus, have found their ways into computer peripherals like keyboards, mice, printers, monitors, etc. The I2C bus and similar arrangements have been adopted by several leading chip manufacturers such as Xicor, SGS-Thomson, Siemens, Intel, TI, Maxim, Atmel, and Analog Devices.
An I2C bus physically comprises two active bus signal lines, conductors or wires and a ground connection. Both of the active wires, having acronyms of SDA and SCL, are bidirectional, where SDA is the serial data line and SCL is the serial clock line. This means that these lines can be driven either by the semiconductor device or an external device. To avoid damage to the semiconductor device; i.e., commonly known as “the fried chip” effect, these bus signal lines typically use open-collector or open-drain (depending on the technology) outputs.
The I2C bus (and similar arrangements) interface is constructed around an input buffer and an open-drain or open-collector transistor. When nothing is happening on the bus, the bus lines are in a logic HIGH state or Asserted state. To put information on the bus, a semiconductor device drives its output transistor, thus pulling the bus to a LOW or negated level. Typically an external PULL UP resistor is then utilized to pull the bus lines back to a logic HIGH state when released by the semiconductor device. When the bus is IDLE (no activity) both lines are at a logic HIGH state. These pull up resistors in the devices are often actually small current sources or may even be nonexistent.
One advantage of this bus concept is that it has a “built-in” bus mastering technique. Whenever the bus is “occupied” by a semiconductor device that is sending a 0, any other semiconductor device looses its capability to master the bus themselves and transmit.
However, the open collector technique has a drawback too. If you have a long bus, it will have a serious effect on the speed of the circuit. Long lines present a capacitive load on the output. Since the pull up resistor is passive, the circuit response time (RC time constant) will be reflected onto the shapes of the signals. The higher the RC time constant for a circuit, the slower the response for the circuit. This is due to the effect that it influences the “sharpness” of the edges of the shapes of the signals for the I2C bus. At a certain point, the logic circuits of a semiconductor die will not be able to distinguish clearly between a logic state 1 and a logic state 0.
However, even this solution fails when faced with a large number of semiconductor devices having long traces as parts of circuits such that the bus capacitance is very high, resistors meeting the pull up current limits cannot produce rise times with the bus performance specification.
One solution to this is the usage of a “bus accelerator” device that detects when the bus voltage begins to rise and produces an extra pulse of pull up current during the edge of a signal shape to ensure that the overall rise time performance specification is met. The bus accelerator device then turns off when the bus voltage stops rising. However, this bus accelerator device expects to see a minimum slew rate at a particular voltage point on the edge of the signal shape before it will turn on, but, in the case of high numbers of devices with long traces as parts of circuits, bus capacitance can be high enough that pull up resistors cannot guarantee meeting this performance specification requirement. In other words, although at zero (0) volts, the slew rate meets the bus accelerator's requirements, at required voltage points, the slew rate performance has dropped off due to the logarithmic nature of the resistor-capacitor (RC time constant) voltage step response.
Another solution that has been used in the prior art is to replace the pull-up resistor with a constant current source. While many different constant current sources have been used, such as current mirrors and other commercially available current sources, all exhibit flaws such as excessive current variability or high dropout voltage, for example.
It would thus be advantageous for a large number of bus devices be able to be connected to a relatively long two-wire serial bus without performance and throughput loss. It would also be advantageous to more accurately control the current utilized to pull up and master the bus.
BRIEF SUMMARY OF THE INVENTION
A two-wire serial (TWS) bus allows bus mastering by any device on the bus utilizing bus pull ups. In systems with long bus lengths or large numbers of devices, rise times suffer unless accelerated. An operational amplifier (Op Amp) controlled current source is utilized to improve slew times for a bus accelerator. The Op Amp provides precise control of the current value and the slew rate or rise time required to meet the stringent requirements of the TWS bus.
A voltage divider is utilized to drive the non-inverting Op Amp input. This drives the voltage of the inverting Op Amp input. This input is tied to the input of a transistor. The transistor base is tied to the Op Amp output and the Op Amp output is tied to the bus. When turned on, current flows through the transistor to the bus until the bus voltage has been driven high, resulting in faster and more precise rise times.
REFERENCES:
patent: 5905389 (1999-05-01), Alleven
patent: 6356140 (2002-03-01), Bell
patent: 6525609 (2003-02-01), Behzad
Hewlett--Packard Development Company, L.P.
Le Don
LandOfFree
Method and apparatus for improving bus capacity does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving bus capacity, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving bus capacity will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3182956