Static semiconductor memory device

Details Static semiconductor memory device Static semiconductor memory device

2002-01-28

2003-12-02

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Flip-flop

C365S156000, C257S368000, C257S903000

Reexamination Certificate

active

06657885

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a static semiconductor memory device (hereinafter simply referred to as an SRAM).
2. Description of the Background Art
Generally, a memory cell for an SRAM is formed of six elements in total including four n type transistors (Q
1
, Q
2
: access transistors, Q
3
, Q
4
: driver transistors) and two p type transistors (Q
5
, Q
6
: load transistors), as shown in FIG.
11
. Two storage nodes
19
a
and
19
b
which are cross coupled have a bistable state of (H, L) or (L, H) and do not change their states if a prescribed power supply voltage is applied.
For data writing, a flip-flop state is set by selecting a word line to open gates (transfer gates) of access transistors Q
1
and Q
2
and forcing a voltage to be applied to a pair of bit lines in accordance with a desired logic value. For data reading, the above mentioned transfer gates are opened and the potentials of storage nodes
19
a
and
19
b
are transmitted to the bit lines. It is noted that, in
FIG. 11
, a cell current
20
is shown which flows from the Low side of storage nodes
19
a
and
19
b
of the memory cell to a ground line (a GND line) through a bit line BL or a complementary bit line /BL from a bit line load (not shown in the drawing) during reading operation.
FIG. 12
shows a layout of a memory cell for an SRAM of the type disclosed in Japanese Patent Laying-Open No. 8-186181, for example. It is noted that a power supply line, ground line, bit line and the like are not shown for the convenience of the drawing.
Referring to
FIG. 12
, a memory cell
1
has n and p wells
2
and
3
provided adjacent to each other. Load transistors Q
5
and Q
6
are formed in n well
2
. Access transistors Q
1
, Q
2
and driver transistors Q
3
, Q
4
are formed in p well
3
.
A pair of word lines
17
a
and
17
b
are provided over memory cell
1
, and a gate of driver transistor Q
3
is connected to p and n type impurity regions through contacts
18
a
and
18
b
, respectively. In addition, a gate of driver transistor Q
4
is connected to p and n type impurity regions through contacts
18
c
and
18
d
, respectively.
As shown in
FIG. 12
, n and p wells
2
and
3
are provided adjacent to each other in a direction in which word lines
17
a
and
17
b
extend, making memory cell
1
longer in the direction of the word lines. Thus, a pitch of a metal interconnection which functions as a bit line or the like increases. In addition, a capacitance between metal interconnections is reduced so that an SRAM capable of operating at a high speed is obtained.
However, memory cell
1
is longer in the direction of word lines
17
a
and
17
b
as described above, resulting in longer word lines
17
a
and
17
b
when such memory cells are arranged in a matrix. Consequently, there arises a problem associated with a signal delay caused by a word line (hereinafter referred to as a “word line delay”).
SUMMARY OF THE INVENTION
The present invention is made to solve the aforementioned problem. It is an object of the present invention to provide an SRAM which has a memory cell including transistor formation regions of different conductivity types provided in a direction of a word line and which is capable of preventing the word line delay.
According to one aspect of the present invention, an SRAM includes a memory cell, a word line and first and second transistor regions. The memory cell includes a pair of access transistors, a pair of driver transistors and a pair of load transistors. The word line is provided for the pair of access transistors. The pair of load transistors are formed in the first transistor region. The second transistor region is provided adjacent to the first transistor region in the direction of the word line and has the pair of access transistors and the pair of driver transistors.
In order to reduce a resistance of the word line to prevent the word line delay, the word line can be formed of metal. In the conventional example shown in
FIG. 12
, however, as two word lines are formed for a single memory cell and p and n wells are arranged in a direction in which the word lines extend, two metal interconnections must be formed in a direction of the shorter sides of the memory cell so as to form the word line of metal. As a result, a pitch between the metal interconnections is made small, whereby the formation of the metal interconnection becomes difficult and a capacitance between the metal interconnections increases. On the other hand, in the present invention, as only one word line is provided, the word line can easily be formed of metal and the resistance of the word line can be reduced. Thus, the word line delay can be prevented.
Preferably, the above mentioned word line is formed of metal. Thereby, the resistance of the word line can be reduced and the word line delay is prevented as described above.
In addition, the SRAM includes first and second memory cells which are arranged in the direction of the word line such that the second transistor regions are adjacent to each other. A metal ground line, which is shared by the first and second memory cells, is provided over the word line in a direction which is orthogonal to the word line. Pairs of metal bit lines for the first and second memory cells are arranged on opposite sides of the metal ground line.
As the metal ground line which are shared by the first and second memory cells is provided in the direction orthogonal to the word line as described above, a cell current for the two memory cells flows to the single metal ground line. Thus, the increase in the potential of the ground line due to the cell current can effectively be prevented.
In addition, a field shield separation (isolation) region may be formed in the memory cell. In this case, preferably, the field shield separation region between the pair of driver transistors is continuously formed in the direction which is orthogonal to the word line to traverse the memory cell.
By forming the field shield separation region as described above, generation of an isolated region in the field shield separation region can effectively be prevented when a plurality of memory cells are arranged in a matrix. When such isolated region is formed, a contact for fixing a potential of the isolated region must be formed, thereby causing a problem that the metal interconnection cannot freely be patterned. In the present invention, however, the metal interconnection can more freely be patterned as compared with the case where the isolated region exists since the isolated region is not generated as described above.
In addition, a first impurity region is shared by one access transistor and one driver transistor and a second impurity region is shared by the other access transistor and the other driver transistor. Preferably, the interval between the ones of the access and driver transistors differs from that between the others of the access and driver transistors.
As shown in
FIG. 1
, for example, a channel width of the driver transistor is generally set greater than that of the access transistor. In this case, if the intervals between the access and driver transistors are different as described above, the driver transistors can be formed offset in the direction which is orthogonal to the word line. Thereby, the memory cell can be reduced in length in the direction of the word line as compared with the case where the driver transistors are arranged spaced by an equal distance from the word line. This is also contributable to the prevention of the word line delay.
According to another aspect, an SRAM of the present invention includes a memory cell, a word line and first and second transistor regions. The memory cell includes a pair of access transistors, a pair of driver transistors and a pair of load transistors, each having a gate. The word line is provided over the memory cell. The pair of load transistors are formed in the first transistor region. The second transistor region is provided adjacent to the first transistor region in the direction in wh

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