Grounded body SOI SRAM cell

Details Grounded body SOI SRAM cell Grounded body SOI SRAM cell

2001-07-25

2003-11-11

Lee, Eddie (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S348000, C257S349000, C257S350000, C257S351000, C257S352000, C257S353000, C257S354000

Reexamination Certificate

active

06646305

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of semiconductor memory devices; more specifically, it relates to a static random access memory (SRAM) formed on a silicon-on-insulator (SOI) substrate and the method of fabricating the SRAM.
BACKGROUND OF THE INVENTION
NFET and PFET devices fabricated in SOI technology offer advantages over bulk devices. The advantages include reduced junction capacitance, reduced junction leakage current, and for fully depleted devices, reduced short channel effect, increased transconductance and reduced threshold voltage (V
T
) sensitivity. However, SOI FETs have a “floating body.” The body or channel region of the FET is formed in an insulated pocket of silicon and is therefore not electrically connected to a fixed potential. One effect of the “floating body” is to lower the V
T
of the device when the body “floats up”. This is a particular problem in a SRAM cell as lowering the V
T
of the devices can cause the relative strengths of devices to change such that the cell flips when the state of the latch is read.
FIG. 1
is a schematic circuit diagram of a CMOS SOI SRAM cell. In
FIG. 1
, an SRAM cell
100
comprises a first input/output (I/O) NFET
105
and a second I/O NFET
110
. SRAM cell
100
further comprises a first latch NFET
115
, a second latch NFET
120
, a first latch PFET
125
and a second latch PFET
130
. The gate of first I/O NFET
105
is coupled to a wordline
135
, the source of the first I/O NFET to a bitline
140
and the drain of the first I/O NFET to a first common node
145
. The gate of second I/O NFET
110
is coupled to a wordline
135
, the source of the second I/O NFET to a bitline-not
155
and the drain of the second I/O NFET to a second common node
160
. The gates of first latch NFET
115
and first latch PFET
125
are coupled to second node
160
. The gates of second latch NFET
120
and second latch PFET
130
are coupled to first node
145
. The source of first latch NFET
115
is coupled to ground (GND) and the drain of the first latch NFET is coupled to first node
145
. The source of second latch NFET
120
is coupled to GND and the drain of the first latch NFET is coupled to second node
160
. Similarly, the source of first latch PFET
125
is coupled to V
DD
and the drain of the first latch PFET is coupled to first node
145
. The source of second latch PFET
130
is coupled to V
DD
and the drain of the first latch PFET is coupled to second node
160
. The bodies of all four NFETs
105
,
110
,
115
, and
120
and both PFETs
125
and
130
are floating.
SRAM cell
100
is written to by writing bitline
140
high and bitline-not
155
low (or vice versa). SRAM cell
100
is read by activating either first I/O NFET
105
(or second I/O NFET
110
) and sensing the current flow from bitline
140
(or bitline-not
155
) to GND. If first I/O NFET
105
“floats up” such that the V
T
of the first I/O NFET becomes lower than the V
T
of first latch NFET
115
(or second I/O NFET
110
“floats up” such that the V
T
Of the second I/O NFET becomes lower than the V
T
of second latch NFET
120
) SRAM cell
100
will become unstable and liable to flip states when read. A device with a low V
T
is a strong device.
In
FIG. 1
, first NFET
105
is designated as T
1
, second I/O NFET
110
as T
2
, first latch NFET
115
as T
3
, second latch NFET
120
as T
4
, first latch PFET
125
as T
5
and second latch PFET
130
as T
6
. This convention is used in all subsequent figures as an aid to reading and comparing the drawings.
FIG. 2
is a partial cross sectional view of a portion of the SRAM cell of FIG.
1
.
FIG. 2
specifically shows the structure and wiring of second I/O NFET
110
and second latch NFET
120
. Formed in a substrate
165
is a buried oxide layer
170
Formed on top of buried oxide layer
170
is a thin silicon layer
175
. Formed in thin silicon layer
175
is an STI
180
. STI
180
extends from a top surface
185
of thin silicon layer
175
, through the thin silicon layer, to buried oxide layer
170
. Formed in thin silicon layer is a source
190
of second latch NFET
120
, a source
195
of second I/O NFET
110
and a common drain
200
. Both second latch NFET
120
and second I/O NFET
110
share common drain
200
. In silicon layer
175
and under a gate
205
of second latch NFET
120
is a second latch NFET body
210
. In silicon layer
175
and under a gate
215
of second I/O NFET
110
is a second I/O NFET body
220
. Source
190
of second latch NFET
120
is coupled to GND and gate
205
is coupled to first node
145
. Source
195
of second I/O NFET
110
is coupled to bitline-not
155
and gate
215
is coupled to wordline
135
. Common drain
200
is coupled to second node
160
.
In
FIG. 2
, second I/O NFET
110
and second latch NFET
120
are illustrated as fully depleted devices. Thus, second latch NFET body
210
and second I/O NFET body
220
are co-extensive with what might otherwise be termed the channel regions of the respective devices. The actual channels themselves are formed in the respective bodies under their respective gates near top surface
185
of thin silicon layer
175
.
FIG. 3
is a plan view of STI, gate, source/drain, contact and first wiring levels of a unit cell of the SRAM cell of FIG.
1
. In
FIG. 3
, the shallow trench isolation (STI) level of SRAM cell
100
is defined by a first thin silicon region
225
A and a second thin silicon region
225
B. The extents of the silicon portions and the STI portions of SRAM cell
100
are set by first and second silicon regions
225
A and
225
B. The gate level is defined by a first gate conductor
240
A, a second gate conductor
240
B, a third gate conductor
240
C and a fourth gate conductor
240
D. First silicon region
225
A is doped N+ where overlapped by an N+ region
250
except where first, second, third and fourth gate conductors
240
A,
240
B,
240
C and
240
D also overlap the first silicon region. The overlap of first silicon region
225
A by first, second, third and fourth gate conductors
240
A,
240
B,
240
C and
240
D defines a first body region
250
A, a second body region
250
B, a third body region
250
C and a fourth body region
250
D respectively. Body regions
250
A,
250
B,
250
C and
250
D are doped P. First body region
250
A divides first silicon region
225
A into a first source region
255
A and a first drain region
255
B. Second body region
250
B divides first silicon region
225
A into a second source region
255
C and a second drain region
255
D. Third and fourth body region
250
C and
250
D further divide first silicon region
225
A into a third source region
255
E.
Second silicon region
225
B is doped P+ where overlapped by a P+ region
260
except where third and fourth gate conductors
240
C and
240
D overlap the second silicon region. The overlap of second silicon region
225
B by third and fourth gate conductors
240
C and
240
D defines a fifth body region
250
E and a sixth body region
250
F respectively. Body regions
250
E and
250
F are doped N. Fifth body region
250
E divides second silicon region
225
B into a third drain region
255
F and a fourth source region
255
G. Sixth body region
250
F further divides second silicon region
225
B into an fourth drain region
255
H.
With reference to
FIG. 1
, first I/O NFET
105
comprises first source region
255
A, first body region
250
A, and first drain region
255
B. Second I/O NFET
110
comprises second source region
255
C, second body region
250
B, and second drain region
255
D. First latch NFET
115
comprises second source region
255
C, third body region
250
C, and third source region
255
E. Second latch NFET
120
comprises third source region
255
E, fourth body region
250
D, and second drain region
255
D. First latch PFET
125
comprises third drain region
255
F, fifth body region
250
E, and fourth source region
255
G. Second latch PFET
130
comprises fourth source region
255
G, sixth body region
250
F, and fourth drain region
255
H.
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