Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-09-11
2003-11-04
Evans, Geoffrey S. (Department: 1725)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C219S121690, C219S121710, C430S313000
Reexamination Certificate
active
06641983
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a printed circuit board, and more particularly, to a method for forming an exposed portion of a circuit pattern in a printed circuit board in which solder lands are formed in a solder resist process of a printed circuit board.
2. Description of the Background Art
FIGS. 1A through 1D
sequentially illustrate a method for forming solder lands in a printed circuit board in accordance with the conventional art. Firstly, in
FIG. 1A
, circuit patterns
2
and solder land circuit patterns
5
are provided on a substrate
3
of a printed circuit board
1
which is preprocessed in the steps prior to the step for a solder resist process such as cleaning and surface roughness treatment.
The solder resist process is a process for coating a protective member on the circuit pattern so that solder and the like are not adhered thereon when a variety of parts mounted on a PCB are connected to the PCB by such a process as soldering. At this time, a portion to be connected with the parts forms a solder land for keeping the circuit pattern in an exposed state, not being coated with a solder resist.
Next, as illustrated in
FIG. 1B
, solder resist ink
7
is coated and temporally dried so that it covers the solder land circuit patterns
5
formed on the substrate
3
. Here, the temporary drying process is a process in which, after coating (printing) a solder mask on a surface, the surface is dried to a certain extent it becomes non-tacky, not being completely hardened. The reason for this process is for the film not to stick fast to the surface during removal of the film, when, in the following processes, an art work film having a circuit pattern is put on the surface and is removed after exposure process, and then a developing process is carried out.
The solder resist
7
prevents the oxidation of the circuit pattern
2
and the solder land circuit pattern
5
, and prevents the circuit pattern
2
and the solder land circuit pattern
5
from being damaged in the following processes.
As described above, after temporally drying the solder resist
7
, an exposure film
9
for forming a solder land is positioned on the printed circuit board
1
, and then is exposed to light. A light transmission portion
10
through which light is transmitted to the position at which a solder land is to be formed in the exposure film
9
, and the transmission portion
10
is formed in the position corresponding to the solder land circuit pattern
5
. Thus, light is transmitted only to the transmission portion
10
, and thereby the solder resist
7
of the portion at which a solder land is to be formed is exposed to light. The above process is illustrated in FIG.
1
C.
When the developing process is carried out after the above exposure process, the solder resist
7
of the portion exposed to light is removed, whereby a solder land S is formed, and thereafter a final hardening process is carried out. The final hardening process is. a process in which the solder resist
7
is completely hardened (molecular bond) after the developing process. The above process is illustrated in FIG.
1
D.
However, the conventional art has the following problem. Firstly, when the exposure process is carried out using the exposure film
9
, a tolerance occurs due to various causes. Thus, considering such a tolerance, the width of the solder land circuit pattern
5
in which the solder land S is formed must be formed wide. That is, considering the decrease of size due to various errors, the solder land is formed to be larger than the required size of the solder land, whereby the size of the solder land to be exposed is maintained constant even if an error occurred.
As described above, the occurrence of error and tolerance is due to the resolution of a CAD/CAM system, position error of the printed circuit board
1
, position error of the exposure film
9
, deviation during exposure of the exposure film
9
, deformation of the film
9
, expansion and twist of the film due to heat in the exposure process, deformation of the size of the printed circuit board
1
, amount of exposure, developing conditions, thickness of the solder resist, temporary drying conditions and the like.
When an error occurs in the formation of the solder land S, the width of the solder land circuit pattern
5
must be increased, considering the position error occurred during the formation of the solder land. That is, as illustrated in
FIG. 2
, considering various errors, the width of the solder land circuit pattern
5
has to be formed as A which is larger than a required width, B. However, the tolerance E corresponding to the portion shown in dotted line at both ends of the solder land circuit pattern
5
is formed due to various errors. If it is possible to precisely form the solder land S, the width of the solder land circuit pattern
5
can be formed as B excepting the portion shown in dotted line at both ends.
Therefore, in the conventional art, the space between both sides of the solder lands s into which circuit lines (traces) of the same size can be inserted is decreased, and the size of the entire PCB is increased as much as the size of the allowable area E. In the case that the same number of lines are required between the solder lands s, the miniaturization of the solder land pitch is restricted, which acts as an obstacle to fabrication techniques of a printed circuit board that is intelligent and has multiple pins. Actually, in the conventional art, an eccentricity of about 65~75 &mgr;m is generated during the formation of the solder land S.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to simplify the process of forming a solder land portion at which a circuit pattern of a printed circuit board is exposed, and increasing the degree of precision of that portion.
It is another object of the present invention to minimize the design amount of tolerance against finishing tolerances by increasing the processing precision of a solder land portion at which a circuit pattern is exposed for thereby highly integrating or miniaturizing the printed circuit board.
To achieve the above objects, there is provided a method for forming an exposed portion of a circuit pattern in a printed circuit board which includes the steps of: forming a insulating layer on a substrate having a circuit pattern; and exposing the circuit pattern by selectively removing a predetermined portion of the insulating layer using a laser.
The present invention further includes the step of hardening the insulating layer before selectively removing the same using a laser.
In accordance with another embodiment of the present invention, there is provided a method for forming an exposed portion of a circuit pattern in a printed circuit board which includes the steps of: forming an insulating layer by coating an insulating material on a substrate having a circuit pattern; selectively removing a predetermined portion of the insulating layer by exposing and developing the same; and exposing the predetermined portion of the insulating layer using a laser.
The present invention further includes the steps of: temporally drying the coated insulating layer; and selectively removing the insulating layer by means of the above exposure and developing processes and then hardening the same.
In the present invention thusly constructed, there is an advantage that a portion such as a solder land in which the circuit pattern is exposed can be formed more precisely by a simple process, thereby highly integrating or miniaturizing the printed circuit board.
Additional advantages, objects and features of the invention will become more apparent from the description which follows.
REFERENCES:
patent: 4766268 (1988-08-01), Uggowitzer
patent: 4961259 (1990-10-01), Schreiber
patent: 5090120 (1992-02-01), Matsumoto
patent: 5134056 (1992-07-01), Schmidt et al.
patent: 5236551 (1993-08-01), Pan
patent: 5403978 (1995-04-01), Drabek et al.
patent: 5665650 (1997-09-01), Lauffer et al.
patent: 5989783 (1999-11-01)
Jang Yong-Soon
Jin Won-Hyeog
Lee Sung-Gue
Evans Geoffrey S.
LG Electronics Inc.
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