Non-volatile electrically alterable semiconductor memory device

Details Non-volatile electrically alterable semiconductor memory device Non-volatile electrically alterable semiconductor memory device

2000-10-25

2003-11-25

Tran, Thien (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257S321000

Reexamination Certificate

active

06653682

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to fast programmable Electrically Erasable Programmable Read-Only Memory devices and method for operating such devices.
BACKGROUND OF THE INVENTION
Nowadays, most Flash memories use Channel Hot Electron Injection (“CHEI”) at the drain side of the memory cell, or Fowler-Nordheim Tunnelling (“FNT”) for programming. The Channel Hot Electron Injection mechanism provides a relatively high programming speed (~10 &mgr;s) at the expense of a high power consumption (~400 &mgr;A/bit) which limits the number of cells that can be programmed simultaneously (so-called page-mode programming) to a maximum of 8 bytes (Y. Miyawaki et al., IEEE J. Solid-State Circuits, vol.27, p.583, 1992). Furthermore, in order to allow a further scaling of the transistor dimensions towards 0.18 &mgr;m and below, supply voltage scaling from 3.3V towards 1.8V also becomes mandatory. This supply voltage scaling is known to degrade the Channel Hot Electron Injection efficiency and, hence, the corresponding programming speed considerably. These memories already use a bitline charge pump to provide a 4-5V drain voltage to the cell during programming and erasing. The problem with this solution is two-fold: (1) since the internally generated programming voltages are not scaled down with respect to the technology generation, it becomes practically impossible to further scale the cell itself, in terms of both vertical (dielectric thicknesses) and lateral (gate length) dimensions; (2) due to the high power needed to trigger the Channel Hot Electron Injection, it becomes harder and harder to supply these voltages on-chip from a high voltage generator or charge pumping circuit. Also, the relative area of the charge pumps and the corresponding high-voltage switching circuitry increases with respect to the useful area of the memory chip.
On the other hand, tunnelling provides slower programming times (~100 &mgr;s) and a low power consumption which allows larger pages (~4 kbit) in order to reduce the effective programming time to 1 &mgr;s/byte (T. Tanaka et al., IEEE J. Solid-State Circuits, vol.29, p.1366, 1994). However, a further improvement is limited by tunnel-oxide scaling limits and by the very high voltages (~15V) needed on chip for Fowler-Nordheim Tunnelling, both compromising device reliability and process scalability.
The recent success of Source-Side Injection (“SSI”) as a viable alternative over Fowler-Nordheim Tunnelling and Channel Hot Electron Injection for Flash programming is mainly due to its unique combination of moderate-to-low power consumption with very high programming speed at moderate voltages. A typical example of such a device relying on Source-Side Injection for programming is the High Injection Metal-Oxide-Semiconductor or HIMOS® memory cell (J. Van Houdt et al., 11th IEEE Nonvolatile Semiconductor Memory Workshop, February 1991; J. Van Houdt et al., IEEE Trans. Electron Devices, vol.ED-40, p.2255, 1993). As also described in the U.S. Pat. Nos. 5,583,810 and 5,583,811, a speed-optimized implementation of the HIMOS® cell in a 0.7-&mgr;m CMOS technology exhibits a 400 nanoseconds programming time while consuming only a moderate current (~35 &mgr;A/cell) from a 5V supply. This result is obtained when biasing the device at the maximum gate current, i.e. at a control-gate voltage (V
cg
) of 1.5V. The corresponding cell area is in the order of 15 &mgr;m
2
for a 0.7-&mgr;m embedded Flash memory technology when implemented in a contactless virtual ground array as described in pending application Ser. No. 08/426,685, incorporated herein by reference. In terms of the feature size F (i.e. the smallest dimension on chip for a given technology), this corresponds to ~30F
2
for a 0.7-&mgr;m technology. This is fairly large as compared to the high density Flash memory concepts which are all in the ~10F
2
range.
However, due to the growing demand for higher densities, also in embedded memory applications like e.g. smart-cards and embedded microcontrollers, a continuous increase in array density and the scaling of the supply voltage become mandatory. This evolution calls for more aggressive cell-area scaling and for low-voltage and low-power operation. In the co-pending application Ser. No. 08/694,812, incorporated herein by reference, a programming scheme is described which reduces the power consumption during the write operation considerably. Also, the used write voltages are expected to scale with the supply voltage V
supply
since the Source-Side Injection mechanism only requires the floating-gate channel to stay in the linear regime for fast programming (see e.g. J. Van Houdt et al., IEEE Trans. Electron Devices, vol. ED-40, p.2255, 1993). Therefore, the necessary Program-Gate voltage V
pg
for fast programming is given by:
V
pg
≈(
V
supply
+V
th
)/
p
  (1)
wherein V
th
is the intrinsic threshold voltage of the floating gate transistor (~0.5V) and p is the coupling ratio from Program Gate to Floating Gate (typically ~50%). According to Eq.(1), V
pg
is thus expected to scale twice as fast as the supply voltage in a first order calculation. It can be concluded that the high programming voltage is scaling very well with the supply voltage and offers enough margin in order for the high voltage circuitry to follow the minimum design rule. These and other features described in the related patents and patent applications indicate the high scalability of the HIMOS® concept in comparison with the traditional cells that use drain multiplication or tunnelling.
However, there are some drawbacks in the HIMOS® cell concept. First, there is a drawback of the additional program gate, which increases the cell area considerably in the case of a double polysilicon technology. Furthermore, since both a control gate and a program gate are formed in the same polysilicon layer, the process requires special polysilicon etching recipes in order to remove the polysilicon stringers between the control gate and the program gate. Another drawback is related to the decoder design. Since the cell is erased with negative gate voltages on the control gate and program gate, as described in the pending application “Method of erasing a Flash EEPROM memory cell optimized for low power consumption”, U.S. Pat. No. 5,969,991 issued Oct. 19, 1999, a pMOS transfer gate is required in the row decoder. During read-out (a program gate voltage is set to zero) and during the write/read deselect operations (a control gate voltage is set to zero), a negative voltage is required to switch the ground potential onto the gates of the array. This in turn requires a small charge pump in the row decoder, which has a small but negative impact on the access time and power consumption. Further, there is a reliability problem associated with the program gate's disturb phenomenon. After a cell has been programmed, the high program gate's programming voltage (typically 9V in a 0.35 &mgr;m technology) can cause discharging of this cell while programming other cells on the same row. Alternatively, erased cells can be slowly programmed because of tunnelling through the tunnel oxide. Further, another problem is due to the appearance of Stress-Induced Leakage Current (“SILC”). When the cell has been written and erased for a large number of times, the tunnel oxide quality is deteriorated in such a way that the application of a small read-out voltage at the drain can cause slow discharging of programmed cells. Even though this is a very small leakage current, it has to be controlled for the entire lifetime of the device that is typically 10 years.
There have been many attempts to obtain a smaller cell using 3 polysilicon layers, as described in a co-pending PCT patent application Ser. No. PCT/BE98/00134, WO 9913513, filed Sep. 9, 1998. Other references to such devices are: (1) U.S. Pat. No. 5,284,784, issued Feb. 8, 1994, to Martin H. Manley; (2) U.S. Pat. No. 5,091,882, issued Feb. 25, 1992, to K. Naruke; (3) U.S. Pat. No. 4,794,565, issued Dec. 27, 1988, to A. T. Wu et al. (4) U.S. Pat. No

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