Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-09-10
2003-11-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06654938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a delay characteristic analyzing method for analyzing the delay characteristic of a custom LSI precisely in the EDA (electronic design automation) for custom LSIs that is used for elaborate designing on the transistor level.
To design a custom LSI that exhibits necessary performance reliably, a transistor-level design technology makes it possible to design a custom LSI by combining a wide variety of transistors freely is required.
To evaluate correctly whether a full custom LSI that has been designed elaborately on the transistor level exhibits necessary performance, a delay characteristic analyzing method for analyzing its delay characteristic very accurately and a delay characteristic analyzing system using such a delay characteristic analyzing method are indispensable.
2. Description of the Related Art
Among the paths connecting an input node and an output node of an LSI, paths along which a signal reaches the output node with a shortest delay time and a longest delay time are called critical paths, respectively. The critical paths and their delay times are part of the important indices that are used to judge whether a designed LSI exhibits intended performance and to identify portions where design modification is needed. The timing analysis methodology is used widely in the custom LSI designing to extract critical paths.
In fields where elaborate transistor-level designing is needed, the dynamic timing analysis using an electrical circuit simulation is performed on the entire net list that indicates a connection between transistors to estimate precisely a delay time of signal transmission along every conceivable path.
However, for LSIs having a large scale, the dynamic timing analysis that is performed on the entire net list is not a realistic method for the following reasons.
First, as the LSI scale increases and the number of input and output nodes increases accordingly, naturally the number of combinations of input signals (hereinafter referred to as “test vectors”) to be prepared for an electrical circuit simulation increases. Second, as the number of output nodes of the LSI increases, the number of combinations of loads that are assumed as loads to be connected to the LSI increases. Third, as the number of transistors constituting the LSI increases, naturally the time that is taken to perform an electrical circuit simulation for each test vector becomes longer and hence an enormous amount of time becomes necessary as a whole to estimate delay times of all the necessary paths.
On the other hand, the static timing analysis can analyze a large-scale net list in a much shorter time than in the above-described dynamic timing analysis, by estimating the delay time in each path according to the delay characteristics of each unit of a circuit, called cell, and the relation between cells. For this reason, the static timing analysis has been used conventionally in such fields as designing of large-scale gate arrays.
However, for the following reasons, it is very difficult to use the static timing analysis itself as a timing analysis methodology for the transistor-level custom LSI designing.
First, to provide the degree of freedom that is necessary in the transistor-level custom LSI designing, it is necessary to construct a large-scale cell library in which a delay characteristic of each of an enormous number of kinds of transistors is registered.
Even if a cell library of such a large scale is prepared, the static timing analysis does not satisfy the accuracy as required in the transistor-level custom LSI designing as long as the static timing analysis employs a method in which the transistor is regarded as a linear resistance and an approximate delay time is determined using an RC product of the linear resistance and a load capacitance. Further, data that is registered in a cell library is just a delay characteristic that was determined in advance for a combination of several typical slew rates and output loads. Therefore, for an input slew rate and an output load that deviate from the above typical values, the accuracy of a delay characteristic obtained by the static timing analysis would be even lower.
Further, in the static timing analysis, a delay time of each path connecting an input node and an output node is estimated individually by accumulating delay times of respective cells on the path. Therefore, in principle, an obtained result does not reflect influences of traveling of signals along other paths on traveling of a signal along the subject path.
For example, consider a case of performing a delay analysis on paths from an input node Al to an output node X in a circuit that is represented by a logic circuit shown in FIG.
25
. Delay time accumulation is performed indiscriminately even for cases where a signal is never transmitted actually along a path to be analyzed as in a case where truth values are inputted at both input nodes A
2
and B
2
or where a false value at the input node A
2
.
Therefore, even an invalid path along which no signal is transmitted actually is detected as a critical path when an obtained delay time is longest or shortest.
To prevent misidentifications such as an invalid path from being detected as a critical path, a method has been proposed in which critical path candidates are extracted based on delay times of respective paths obtained by the static timing analysis and an electrical circuit simulation is performed by generating test vectors for those paths.
However, determining a true critical path using the above method still requires much labor and processing time.
This is for the following reason. According to simple calculation, the number of test vectors that are necessary to determine a correct delay time for one critical path candidate is equal to the square of a number obtained by subtracting 1 from the number n of external input terminals, that is, (n−1)
2
. In addition, as the number of stages of transistors along the path candidate increases, an electrical circuit simulation for each test vector comes to take longer time; the total processing time becomes very long. Naturally, the number of test vectors can be decreased by using an automatic test vector generation method. The advantage of the automatic test vector generation method may not be fully utilized in a case where the subject LSI has a complex circuit configuration containing many pass transistors and has many external input terminals.
In the conventional dynamic timing analysis, an electrical circuit simulation is performed on the entire circuit. And in the conventional static timing analysis, a subject of delay characteristic analysis is a path from an input terminal to an output terminal.
Therefore, whichever delay characteristic analyzing method is used, when the design of a custom LSI is modified, a dynamic timing analysis is performed on the entire circuit or a static timing analysis is performed on every conceivable path in the same manner as in the case of analyzing a new net list irrespective of the range where the modification has influence. It is impossible to quickly cope with a partial modification to a net list.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a delay characteristic analyzing method capable of shortening the processing time while maintaining a high degree of freedom of LSI designing and high accuracy of critical path determination in transistor-level full custom LSI designing.
Another object of the invention is to provide a delay characteristic analyzing method that enables quick and precise delay characteristic analysis by utilizing a result of an analysis that was performed on a circuit before the change where there is partial modification of a net list (the circuit design or the conditions relating to signal transmission) in full custom LSI designing.
Another object of the invention is to obtain very quickly an analysis result with incomparably higher accuracy than a conventional, simple timing analysis by analyzing the
Fujitsu Limited
Lin Sun James
Smith Matthew
Staas & Halsey , LLP
LandOfFree
Delay characteristic analyzing method and delay... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Delay characteristic analyzing method and delay..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Delay characteristic analyzing method and delay... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3180822