Strontium nitride or strontium oxynitride gate dielectric

Details Strontium nitride or strontium oxynitride gate dielectric Strontium nitride or strontium oxynitride gate dielectric

2000-09-01

2003-02-11

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S410000, C257S411000, C257S310000, C438S216000, C438S261000, C438S287000

Reexamination Certificate

active

06518634

ABSTRACT:

FIELD OF THE INVENTION
The present invention is related to the field of semiconductor fabrication and more particularly to a semiconductor device with a strontium nitride or strontium oxynitride gate dielectric and an associated process for forming the device.
RELATED ART
In the field of semiconductor fabrication, the use of dielectric materials with a high dielectric constant (high K materials) is well known. High K materials enable the use of thicker dielectric layers in MOS transistors while maintaining the required capacitance. A thicker dielectric layer is typically desirable to reduce gate leakage current thereby reducing the power consumption of the device. In many applications, such as wireless applications, the power consumption is a significant constraint on the ability to prolong the operation/standby time of a portable device.
The use of strontium as an element in a high K material has been typically limited to strontium titanate (SrTiO3), also referred to as STO. Typically, STO is formed with a molecular beam epitaxy process. Because of a mismatch between the STO lattice constant and the lattice constant of the underlying silicon substrate, it is typically necessary to include a buffer or template layer between the STO and the silicon. A conventional template layer for epitaxial STO processes is strontium oxide (SrO). Unfortunately, the use of an oxygen bearing template layer undesirably results in the formation of silicon dioxide at the upper surface of the silicon substrate. The lower dielectric constant of the silicon dioxide undesirably increases the effective oxide thickness (EOT) of the dielectric stack. In addition, epitaxial STO deposition rates are typically less than one monolayer per minute. To form a sufficiently thick epitaxial STO layer typically requires in the range of approximately 30 minutes to 60 minutes per wafer. The throughput restraints imposed by such a process are prohibitive in most manufacturing environments. It would therefore be desirable to implement a gate dielectric process utilizing strontium that did not include an epitaxial process.


REFERENCES:
patent: 1011149 (2000-06-01), None
Jean Gaude et al.: “:Le systeme strontium-azote. II. Sur une nouvelle combinaison du strontium et de l'azote;” Revue de Chimie Mineral, t. 8, 1971, pp. 287-299; Manuscrit recu le 30 Nov. 1970.

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